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Brnch:fpga Trgt:chisel
Matthew Feldman edited this page May 1, 2018
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Spatial commit
commit f2ba4e7c5d88539b973a1ea96c287629636a1f4a
Merge: 88a5d4b c679883
Author: Matthew Feldman <mattfel@stanford.edu>
Date: Tue May 1 16:01:11 2018 -0700
Merge remote-tracking branch 'origin/develop' into fpga
commit c6798839f7e655ee0abdd816c3974c25c7b8b001
Author: Raghu Prabhakar <raghup@sambanovasystems.com>
Date: Wed Apr 25 11:41:49 2018 -0700
Update apps ptr
M apps
commit c0d1517b6e50fcac9be168fc7dd593ae5d3d2fa9
Merge: 4ee8c37 eb2e937
Author: Raghu Prabhakar <raghup@sambanovasystems.com>
Date: Wed Apr 25 11:27:43 2018 -0700
Merge branch 'develop' into asic
commit eb2e93764081c28d355dc393c2e7585018c1138a
Merge: 17694d8 ca63b75
Author: Matthew Feldman <mattfel@stanford.edu>
Date: Mon Apr 23 10:33:11 2018 -0700
Merge remote-tracking branch 'origin/fpga' into develop
commit 17694d8c4ccdf4d3f06b11269232c3a917053d8b
Merge: b7dcf10 acb4805
Author: Matthew Feldman <mattfel@stanford.edu>
Date: Tue Apr 17 13:35:11 2018 -0700
Merge remote-tracking branch 'origin/fpga' into develop
commit b7dcf10e74ec83da901371afcfcc5e53c92cd069
Merge: 6b5a110 a33f38a
Author: Matthew Feldman <mattfel@stanford.edu>
Date: Tue Apr 17 10:11:11 2018 -0700
Merge remote-tracking branch 'origin/fpga' into develop
commit 6b5a1104d02812c0e1d7786e5fdbd6c2523e4c5f
Author: Matthew Feldman <mattfel@stanford.edu>
Date: Fri Apr 13 17:39:31 2018 -0700
auto merge
M apps
commit 9c6c14b5d2fd917253c6d442ea2bc92140f4de20
Merge: 91a0c1c 57bc676
Author: Matthew Feldman <mattfel@stanford.edu>
Date: Fri Apr 13 17:39:30 2018 -0700
Merge remote-tracking branch 'origin/fpga' into develop
commit 91a0c1c8c76a6186b8edadde9cccbceeda1a4c16
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Thu Apr 12 13:14:38 2018 -0700
track original apps
M apps
commit 0ee0e567878c5bfcf8e174e2e107e909f860769b
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Thu Apr 12 13:13:50 2018 -0700
track pir apps
M apps
M spatial/core/src/spatial/codegen/pirgen/PIRCodegen.scala
D spatial/core/src/spatial/codegen/pirgen/PIRControlAnalyzer.scala
M spatial/core/src/spatial/codegen/pirgen/PIRTraversal.scala
commit 0bbcdc4cd8b73027afcf60e941d96bc988c59f00
Merge: bbb676f 7d8a2af
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Thu Apr 12 13:13:04 2018 -0700
fix conflicts merging develop
commit bbb676fce5139837c9ee103f48add945a6f7be13
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Wed Apr 11 17:54:16 2018 -0700
add emit bufferSize in GenMem
M spatial/core/src/spatial/codegen/pirgen/PIRGenMem.scala
commit cec5ff752b5a77b0e31a42d04263a5935300d6f7
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Mon Apr 2 23:52:46 2018 -0700
minor changes to pir codegen
M spatial/core/src/spatial/codegen/pirgen/PIRGenMem.scala
M spatial/core/src/spatial/codegen/pirgen/PIRGenOp.scala
commit 7d8a2afae8b1cd5b6dc90aa0feb3e1b5a75c8faa
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Mon Apr 2 23:48:42 2018 -0700
merge pir
M spatial/core/src/spatial/codegen/pirgen/PIRStructAnalyzer.scala
commit 0c0f9ea318821e87da7ad08daa6552939e6e52aa
Merge: b115bc1 b68fadf
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Mon Apr 2 23:01:47 2018 -0700
merge pir
commit b115bc190ebe9506baed581bfeb16a18538d15f4
Author: David Koeplinger <dkoeplinger@gmail.com>
Date: Mon Apr 2 22:01:25 2018 -0700
Fix bug with metapipeline check
M spatial/core/src/spatial/utils.scala
commit 4ee8c3719b991fe9b9ddb29d35b47eec7bf6bf0c
Author: wshwang <wshwang@uw.edu>
Date: Wed Mar 14 01:23:44 2018 -0700
optimize powers-of-2 constant multiplication with bit select
M spatial/core/resources/chiselgen/template-level/fringeASIC/bigIP/BigIPASIC.scala
commit ec3f3ca246ac09c0df0bfe208bd6a2ce5159ed9a
Author: wshwang <wshwang@uw.edu>
Date: Tue Mar 13 15:41:46 2018 -0700
add some comments
M spatial/core/resources/chiselgen/template-level/fringeASIC/bigIP/BigIPASIC.scala
commit 38f458e32fc552f283b75875ed6bec438b50301a
Merge: b41521a a5b9206
Author: wshwang <wshwang@uw.edu>
Date: Tue Mar 13 15:22:44 2018 -0700
Merge branch 'develop' of https://github.com/stanford-ppl/spatial-lang into asic
commit b41521a4a75eca8cd2ad064aa7c249af1bfd63f3
Author: wshwang <wshwang@uw.edu>
Date: Tue Mar 13 15:21:31 2018 -0700
change log2Up (deprecated) to log2Ceil everywhere in BigIPASIC
M spatial/core/resources/chiselgen/template-level/fringeASIC/bigIP/BigIPASIC.scala
commit 35cc840d66014e2bbfa33a4cace991cf066823e5
Author: wshwang <wshwang@uw.edu>
Date: Tue Mar 13 15:11:50 2018 -0700
use log2Up everywhere in BigIPASIC
M spatial/core/resources/chiselgen/template-level/fringeASIC/bigIP/BigIPASIC.scala
commit 99f4395117ecd803a83f6f89074e04d6bea444a3
Author: wshwang <wshwang@uw.edu>
Date: Tue Mar 13 15:09:16 2018 -0700
fix power-of-2 divides and mods optimization -- apparently chisel thinks log2Up(1) == log2Down(1) == 1
M spatial/core/resources/chiselgen/template-level/fringeASIC/bigIP/BigIPASIC.scala
commit 6d26b40af3c7a66c89aeaed850de3642a7eb407d
Author: Raghu Prabhakar <raghup17@gmail.com>
Date: Sat Mar 10 01:07:11 2018 -0800
Handle case in div optimization where divisor's width is lesser than shift amount
M spatial/core/resources/chiselgen/template-level/fringeASIC/bigIP/BigIPASIC.scala
commit 5820b349b08545f38517c25b94dd33e8e4a8f133
Author: Raghu Prabhakar <raghup17@gmail.com>
Date: Fri Mar 9 22:49:03 2018 -0800
Optimize power-of-2 divides and mods
M spatial/core/resources/chiselgen/template-level/fringeASIC/bigIP/BigIPASIC.scala
commit 802ba427135ce19746e0621bea77eab3691bb887
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Wed Mar 7 17:19:15 2018 -0800
use binary string in constant instead of convert it into integer
M spatial/core/src/spatial/codegen/pirgen/PIRGenOp.scala
commit e723695424d467ab815fdc9bc54220041e97561c
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Tue Mar 6 00:13:14 2018 -0800
bug fixes to codegen quote
M spatial/core/src/spatial/codegen/pirgen/PIRCodegen.scala
M spatial/core/src/spatial/codegen/pirgen/PIRFileGen.scala
M spatial/core/src/spatial/codegen/pirgen/PIRGenMem.scala
M spatial/core/src/spatial/codegen/pirgen/PIRGenOp.scala
M spatial/core/src/spatial/codegen/pirgen/PIRGenSpatial.scala
M spatial/core/src/spatial/codegen/pirgen/PIRLogger.scala
M spatial/core/src/spatial/codegen/pirgen/PIRStructAnalyzer.scala
M spatial/core/src/spatial/codegen/pirgen/PIRTraversal.scala
commit fafbb2866eee486a046510df19a79dacf373065c
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Mon Mar 5 22:52:43 2018 -0800
minor changes in codegen header
M spatial/core/src/spatial/codegen/pirgen/PIRFileGen.scala
commit 515dca6865ab7038065e3c682646f298d844e0e7
Author: wshwang <wshwang@uw.edu>
Date: Sat Mar 3 23:43:34 2018 -0800
fix posedge triggered SRAMVerilogSim and remove race condition weirdness at SystemVerilog/C interface
M spatial/core/resources/chiselgen/template-level/fringeVCS/SRAMVerilogSim.v
M spatial/core/resources/chiselgen/template-level/fringeVCS/Top-harness.sv
commit 126a46aad48658f3a1835e0e6f24b90372924854
Merge: a37006a c0e0398
Author: wshwang <wshwang@uw.edu>
Date: Thu Mar 1 21:31:20 2018 -0800
Merge commit 'c0e0398' into asic
commit 6eeb5021f801ae1e68dc2e3635f29fa744c59392
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Wed Feb 21 13:56:21 2018 -0800
add operation lowering for fix conversion
M spatial/core/src/spatial/codegen/pirgen/PIRGenMem.scala
M spatial/core/src/spatial/codegen/pirgen/PIRGenOp.scala
M spatial/core/src/spatial/codegen/pirgen/PIRTraversal.scala
commit 2d9910b75f262f6338c175213ce2bfa2f4bfe6a5
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Sun Feb 18 23:47:41 2018 -0800
move unrolling of reduction into PIRCompiler
M spatial/core/src/spatial/codegen/pirgen/PIRFileGen.scala
M spatial/core/src/spatial/codegen/pirgen/PIRGenMem.scala
M spatial/core/src/spatial/codegen/pirgen/PIRGenOp.scala
commit 35a61c4a5df27b4c716863383aa72fe74a93c8d4
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Sat Feb 17 16:15:24 2018 -0800
bug fixes to usage of getDispatches
M spatial/core/src/spatial/codegen/pirgen/PIRGenMem.scala
commit 3a9997968261ea0580c2cca324ef2ceb8c657f29
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Thu Feb 15 17:07:31 2018 -0800
breaking files
M spatial/core/src/spatial/Spatial.scala
M spatial/core/src/spatial/codegen/pirgen/PIRCodegen.scala
A spatial/core/src/spatial/codegen/pirgen/PIRGenController.scala
A spatial/core/src/spatial/codegen/pirgen/PIRGenCounter.scala
A spatial/core/src/spatial/codegen/pirgen/PIRGenDummy.scala
A spatial/core/src/spatial/codegen/pirgen/PIRGenFringe.scala
A spatial/core/src/spatial/codegen/pirgen/PIRGenMem.scala
A spatial/core/src/spatial/codegen/pirgen/PIRGenOp.scala
commit cea39bfe032f6219beda135652c714387392648d
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Thu Feb 15 16:59:20 2018 -0800
remove legacy code
D spatial/core/src/spatial/codegen/pirgen/PIR.scala
D spatial/core/src/spatial/codegen/pirgen/PIRAllocation.scala
D spatial/core/src/spatial/codegen/pirgen/PIRAreaModelHack.scala
M spatial/core/src/spatial/codegen/pirgen/PIRCodegen.scala
M spatial/core/src/spatial/codegen/pirgen/PIREnum.scala
D spatial/core/src/spatial/codegen/pirgen/PIRGenController.scala
D spatial/core/src/spatial/codegen/pirgen/PIRHackyLatencyAnalyzer.scala
D spatial/core/src/spatial/codegen/pirgen/PIRHackyModelingTraversal.scala
D spatial/core/src/spatial/codegen/pirgen/PIRHackyRetimer.scala
M spatial/core/src/spatial/codegen/pirgen/PIRLogger.scala
M spatial/core/src/spatial/codegen/pirgen/PIRMetadata.scala
D spatial/core/src/spatial/codegen/pirgen/PIROptimizer.scala
D spatial/core/src/spatial/codegen/pirgen/PIRScheduler.scala
D spatial/core/src/spatial/codegen/pirgen/PIRSplitter.scala
D spatial/core/src/spatial/codegen/pirgen/PIRSplitting.scala
M spatial/core/src/spatial/codegen/pirgen/PIRTraversal.scala
D spatial/core/src/spatial/codegen/pirgen/Partitions.scala
D spatial/core/src/spatial/codegen/pirgen/PlasticineLatencyModel.scala
M spatial/core/src/spatial/codegen/pirgen/package.scala
commit 5c36a8966bca5e09b12dedffb5f619d4bb719cd1
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Wed Feb 14 15:04:40 2018 -0800
bug fixes with reduction stage generation
M spatial/core/src/spatial/codegen/pirgen/PIRCodegen.scala
commit 2e2d3dfd603249793a3081dd71656b8fb75554cb
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Tue Feb 13 18:33:24 2018 -0800
track pir apps
M apps
commit 6a9ec8b8f432cc10327750c91d97b0bc5c6175b1
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Tue Feb 13 18:31:41 2018 -0800
change struct analyzer to not create new symbol if struct only contains a single element
M spatial/core/src/spatial/codegen/pirgen/PIRCodegen.scala
M spatial/core/src/spatial/codegen/pirgen/PIRLogger.scala
M spatial/core/src/spatial/codegen/pirgen/PIRStructAnalyzer.scala
commit 40b627f667e846f3fee5202ff422dfee8f9653bd
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Mon Feb 12 23:09:48 2018 -0800
fix RegFile not generated for different outer banks
M spatial/core/src/spatial/codegen/pirgen/PIRCodegen.scala
commit f0681c39ea565c76147c8abc6df6fa324b904105
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Mon Feb 12 23:01:33 2018 -0800
add more op node backends. Refactor PIRMemoryAnalyzer.scala to analyze all types of memory
M spatial/core/src/spatial/codegen/pirgen/PIRCodegen.scala
M spatial/core/src/spatial/codegen/pirgen/PIREnum.scala
M spatial/core/src/spatial/codegen/pirgen/PIRFileGen.scala
M spatial/core/src/spatial/codegen/pirgen/PIRGenSpatial.scala
M spatial/core/src/spatial/codegen/pirgen/PIRLogger.scala
M spatial/core/src/spatial/codegen/pirgen/PIRMemoryAnalyzer.scala
M spatial/core/src/spatial/codegen/pirgen/package.scala
commit a37006a1b2d010f47ea878275449382586dffd47
Merge: b2423ed 5695c10
Author: wshwang <wshwang@uw.edu>
Date: Mon Feb 12 18:02:56 2018 -0800
Merge branch 'develop' of https://github.com/stanford-ppl/spatial-lang into asic
commit b2423edcb27f002a10afc3c2e47604452b9659da
Merge: d63025a fb93128
Author: wshwang <wshwang@uw.edu>
Date: Sat Feb 10 16:53:49 2018 -0800
merge with develop
commit f7884d5c1b3effdc32e61f5ab498ad8cee15e4bd
Merge: 692ba89 0bae019
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Mon Feb 5 19:00:44 2018 -0800
tracking pir apps
commit 692ba89a97cfdc24d36c013e8ed3565a9e2b0401
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Mon Feb 5 18:58:20 2018 -0800
add different type of controller. Fix reduction generation
M spatial/core/src/spatial/codegen/pirgen/PIRCodegen.scala
commit d63025ae95a749ac2e2fff25c930f2fcafee031d
Author: wshwang <wshwang@uw.edu>
Date: Tue Jan 30 20:28:44 2018 -0800
disable debug signals in Fringe for the asic target
M spatial/core/resources/chiselgen/template-level/fringeHW/FringeGlobals.scala
commit 63e232430d6559b01d91a9045adcec9a35786940
Author: raghu <raghup17@gmail.com>
Date: Sun Jan 28 23:33:22 2018 -0800
Reduce FIFO size to 2 entries (16 elements/entry * 2)
M spatial/core/resources/chiselgen/template-level/fringeHW/Fringe.scala
commit f6efbf112bf5a1900942a00156b9d16ffd203b54
Author: wshwang <wshwang@uw.edu>
Date: Thu Jan 25 23:05:23 2018 -0800
route flow signal to asic flop arrays and retime shift registers
M spatial/core/resources/chiselgen/template-level/fringeASIC/build/RetimeShiftRegister.sv
M spatial/core/resources/chiselgen/template-level/fringeVCS/SRAMVerilogSim.v
commit 27fed322afddbee3cec5d68ba03eb6ee48a73e40
Author: wshwang <wshwang@uw.edu>
Date: Thu Jan 25 22:12:49 2018 -0800
update flop arrays to use designware modules when possible
M spatial/core/resources/chiselgen/template-level/fringeVCS/SRAMVerilogSim.v
commit 62627cb2923cc0020bfcebe84e46bda48ff6f0a9
Author: wshwang <wshwang@uw.edu>
Date: Thu Jan 25 22:11:32 2018 -0800
update designware dividers, multipliers, and flop arrays
M spatial/core/resources/chiselgen/app-level/Makefile
M spatial/core/resources/chiselgen/template-level/fringeASIC/bigIP/ASICBlackBoxes.scala
M spatial/core/resources/chiselgen/template-level/fringeASIC/bigIP/BigIPASIC.scala
M spatial/core/resources/chiselgen/template-level/fringeASIC/build/designware_divmod.v
M spatial/core/resources/chiselgen/template-level/fringeASIC/build/designware_mult.v
commit 1bf8de667d750673361bc3ef90930c70361901e0
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Thu Jan 25 18:04:36 2018 -0800
change staticBankOf to take key and instId as key
M spatial/core/src/spatial/codegen/pirgen/PIRAllocation.scala
M spatial/core/src/spatial/codegen/pirgen/PIRCodegen.scala
M spatial/core/src/spatial/codegen/pirgen/PIRMemoryAnalyzer.scala
M spatial/core/src/spatial/codegen/pirgen/PIRMetadata.scala
commit 4dd517290bc64327ce49c7b1ce456333b9097a31
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Thu Jan 25 00:15:39 2018 -0800
update codegen backend for more nodes
M spatial/core/src/spatial/codegen/pirgen/PIRCodegen.scala
commit df576181a298963b989cac600c9771ebed193355
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Tue Jan 16 20:45:39 2018 -0800
working on PIRGen with simplified IR
M apps
M spatial/core/src/spatial/codegen/pirgen/PIRCodegen.scala
A spatial/core/src/spatial/codegen/pirgen/PIRControlAnalyzer.scala
D spatial/core/src/spatial/codegen/pirgen/PIRDSE.scala
M spatial/core/src/spatial/codegen/pirgen/PIRFileGen.scala
M spatial/core/src/spatial/codegen/pirgen/PIRGenController.scala
M spatial/core/src/spatial/codegen/pirgen/PIRMetadata.scala
D spatial/core/src/spatial/codegen/pirgen/PIRPrintout.scala
D spatial/core/src/spatial/codegen/pirgen/PIRStats.scala
commit b68fadf6b6cc18f193847457ecfd2f0a4b276dee
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Thu Dec 7 18:12:29 2017 -0800
add error message when multiple inner dimensions are parallelized for plasticine. Bug fix in PIRAllocation
M spatial/core/src/spatial/codegen/pirgen/PIRAllocation.scala
M spatial/core/src/spatial/codegen/pirgen/PIRMemoryAnalyzer.scala
M spatial/core/src/spatial/codegen/pirgen/PIRMetadata.scala
commit b1b30389e13d0bcf0c11e9b8a1cfb02e517b20be
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Thu Nov 30 17:49:53 2017 -0800
change inner dim analysis to per instance basis for pir
M spatial/core/src/spatial/codegen/pirgen/PIRAllocation.scala
M spatial/core/src/spatial/codegen/pirgen/PIRMemoryAnalyzer.scala
M spatial/core/src/spatial/codegen/pirgen/PIRMetadata.scala
commit adcb6e1ea158ce9b0db6f997588bc6f0a7e01544
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Thu Nov 30 16:46:56 2017 -0800
bug fixes to struct and memory analyzer
M spatial/core/src/spatial/codegen/pirgen/PIRMemoryAnalyzer.scala
M spatial/core/src/spatial/codegen/pirgen/PIRStructAnalyzer.scala
commit df7373891867be4bcc2c41400c484b16f2dbd25e
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Thu Nov 30 15:25:13 2017 -0800
improve regression scripts
M apps
commit a5893425872e5b4f6b0575360f57096eb3e1b3d3
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Thu Nov 30 15:22:21 2017 -0800
remove legacy IR CUContext and LocalRef in PIR
M spatial/core/src/spatial/codegen/pirgen/PIR.scala
M spatial/core/src/spatial/codegen/pirgen/PIRAreaModelHack.scala
M spatial/core/src/spatial/codegen/pirgen/PIRGenController.scala
M spatial/core/src/spatial/codegen/pirgen/PIRLogger.scala
M spatial/core/src/spatial/codegen/pirgen/PIROptimizer.scala
M spatial/core/src/spatial/codegen/pirgen/PIRScheduler.scala
M spatial/core/src/spatial/codegen/pirgen/PIRSplitter.scala
M spatial/core/src/spatial/codegen/pirgen/PIRSplitting.scala
M spatial/core/src/spatial/codegen/pirgen/PIRTraversal.scala
M spatial/core/src/spatial/codegen/pirgen/Partitions.scala
M spatial/core/src/spatial/codegen/pirgen/package.scala
commit f5c7fddc347e31fdb7846dc7df205733ce291eb8
Merge: f6d66e6 c0acfe6
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Wed Nov 29 14:28:46 2017 -0800
track pir
commit f6d66e6848bfbc81aac33ced5e4d2d783ae3c72e
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Wed Nov 29 14:26:08 2017 -0800
track apps
M apps
commit 8bcf05fb5cbde054049f2e2a89e71080f713563a
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Wed Nov 15 23:12:44 2017 -0800
bug fixes to PIROptimizer
M spatial/core/src/spatial/codegen/pirgen/PIROptimizer.scala
M spatial/core/src/spatial/codegen/pirgen/PIRSplitting.scala
M spatial/core/src/spatial/codegen/pirgen/package.scala
commit 620ebe083a1cd1adc4a61a0f7b0e86e3c598a893
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Wed Nov 15 21:58:42 2017 -0800
bug fixes to optimizer and printout
M spatial/core/src/spatial/codegen/pirgen/PIROptimizer.scala
M spatial/core/src/spatial/codegen/pirgen/PIRPrintout.scala
M spatial/core/src/spatial/codegen/pirgen/PIRSplitting.scala
M spatial/core/src/spatial/codegen/pirgen/PIRTraversal.scala
M spatial/core/src/spatial/codegen/pirgen/package.scala
commit 33273354b726fce91aac04cfbd98cee87c5d7245
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Wed Nov 15 15:34:30 2017 -0800
refactor collect function
M spatial/core/src/spatial/codegen/pirgen/PIR.scala
M spatial/core/src/spatial/codegen/pirgen/PIRCodegen.scala
M spatial/core/src/spatial/codegen/pirgen/PIRDSE.scala
M spatial/core/src/spatial/codegen/pirgen/PIRLogger.scala
M spatial/core/src/spatial/codegen/pirgen/PIROptimizer.scala
M spatial/core/src/spatial/codegen/pirgen/PIRPrintout.scala
D spatial/core/src/spatial/codegen/pirgen/PIRRetiming.scala
M spatial/core/src/spatial/codegen/pirgen/PIRSplitting.scala
M spatial/core/src/spatial/codegen/pirgen/PIRStructAnalyzer.scala
M spatial/core/src/spatial/codegen/pirgen/PIRTraversal.scala
M spatial/core/src/spatial/codegen/pirgen/Partitions.scala
M spatial/core/src/spatial/codegen/pirgen/package.scala
commit 711dc886287b7da0a815acce24eb88572e0d933d
Author: Yaqi Zhang <hsbzyq@gmail.com>
Date: Tue Nov 14 22:13:33 2017 -0800
refactor struct handling into a saperate analysis
M spatial/core/src/spatial/codegen/pirgen/PIRAllocation.scala
M spatial/core/src/spatial/codegen/pirgen/PIRCodegen.scala
M spatial/core/src/spatial/codegen/pirgen/PIRMetadata.scala
A spatial/core/src/spatial/codegen/pirgen/PIRStructAnalyzer.scala
M spatial/core/src/spatial/codegen/pirgen/PIRTraversal.scala
M spatial/core/src/spatial/codegen/pirgen/package.scala
Argon commit
commit b19da8cf1ac81cd62f33c07711c290306d5e0edb
Author: Matthew Feldman <mattfel@stanford.edu>
Date: Fri Mar 16 11:56:26 2018 -0700
fix mistake in ++
M core/src/argon/lang/Array.scala
Virtualized commit
commit 05f6c52d98f892ee732cf8c43cd6c336dabc9bf4
Author: Matthew Feldman <mattfel@stanford.edu>
Date: Mon Mar 12 17:51:44 2018 -0700
update build.sbt
M build.sbt
Spatial-Apps commit
commit 53fb35903c626e1b9f5e774a4fb851302f817991
Merge: 7fd5523 b6b9a31
Author: raghu <raghup17@gmail.com>
Date: Wed Sep 13 17:29:50 2017 -0700
Merge branch 'develop' of https://github.com/stanford-ppl/spatial-apps into develop
commit b6b9a31d2499937c641d7e933dca9dc237ea4cb9
Author: Raghu Prabhakar <raghup17@gmail.com>
Date: Sat Sep 9 23:55:31 2017 -0700
Params change to SimpleTileLoadStore
M src/UnitTests.scala
commit 1aa8ebd9a899424bba73b02e4e34e5ce082b4901
Author: Raghu Prabhakar <raghup17@gmail.com>
Date: Thu Sep 7 18:31:57 2017 -0700
Add comma between staging options
M src/BandwidthTests.scala
Creation Time- 2018-05-01_16-01-24 | Status- debug | Type- chisel | tests- all | User- mattfel | Origin- london | Destination- london | Branch- fpga | Spatial- f2ba4 | Argon- b19da | Virtualized- 05f6c | Spatial-apps- 53fb3