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Add basic code intelligence for Pascal, Verilog, and VHDL #200
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creachadair
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chrismwendt
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Jan 28, 2020
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While trying this out I found some samples:
- Verilog https://sourcegraph.com/github.com/ZipCPU/wbuart32/-/blob/bench/verilog/helloworld.v
- VHDL https://sourcegraph.com/github.com/xesscorp/VHDL_Lib@master/-/blob/HostIoComm.vhd
It's ok to merge this in before adding language entries to https://github.com/sourcegraph/sourcegraph/blob/3a1dd8ccd49175ef2ed47dabe85d2e0543ce6c47/shared/src/languages.ts#L40
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January 28, 2020 10:02
A tool to partly automate seeding basic intel support, by parsing universal-ctags output for supported languages. A human must vet the output since ctags does not have enough data to infer comment style or derive applicable filtering rules.
Fold together Verilog and SystemVerilog since the syntax is the same.
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creachadair
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Thanks, your Verilog example was nicer than the one I was using. |
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chrismwendt
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Jan 28, 2020
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Here's an ethernet mac written in verilog if needed. Bunch of different VHDL library elements |
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For the results of this change to be visible in the UI, you must also sync Sourcegraph past https://github.com/sourcegraph/sourcegraph/pull/8079.
Fixes https://github.com/sourcegraph/sourcegraph/issues/4915.