Fix type of C_DIV for cv32e40p_fp_wrapper#86
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bluewww merged 1 commit intopulp-platform:masterfrom Jun 10, 2022
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Required for synthesis with Vivado 2020.2
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After !77 This PR replaces legacy `RI5CY` with `CV32E40P` in either the SoC (FC controller) and the cluster (8 core instances) **HW (RTL)**: - [x] Replace cv32e40p with OBI adapter into SoC - [x] Add FPU wrapper into SoC using APU connection. FPU is now instantiated in `fc_subsystem` - [x] Replace cv32e40p with OBI adapter into Cluster - [x] Add `pulp_clock_gating` tech cell for ASIC, disable clock gating for FPGA (as in RI5CY) **[TODO: do it properly without using `ifdef`]** (#85) - [x] Add one [performance counters test](https://github.com/pulp-platform/regression_tests/tree/cv32perf_counters/perf_counters) in assembly for cv32 to be executed with pulp-runtime **SW**: Main SW changes concerns: 1. Different mapping of the HW loops (`Xpulp` extensions) 2. Different structure and mapping of the performance counters 3. Enable clint timer irq (Freertos and RTL) - [x] Change `PULP RISCV GCC toolchain` version used in the CI with cv32e40p target with: `/usr/pack/riscv-1.0-kgf/pulp-gcc-2.2.0` - [x] Update `pulp-runtime` with cv32e40p target with: `v0.0.9` - [x] Update `FreeRTOS` version with cv32e40p target with: `570b2c1c` **MISC** - [x] Update README - [x] Update CHANGELOG - The testset has been previously overhauled in !63 and !65. In particular !63 removed some tests that used the legacy pulp-sdk and RI5CY and were not a fit anymore with cv32 Within this project boundary, there exits three issues tracked in #87, #86 and #85 that will be addressed in separate MRs Fixes #59 #60 #84
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Required for synthesis with Vivado 2020.2
This is the same error as in pulp-platform/cv32e40p#2