ex_stage: Fix type of C_DIV#2
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bluewww merged 1 commit intopulpissimo-v3.4.0-devfrom Mar 30, 2021
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Without this explicit type annotation, Vivado 2020.2 fails to synthesize this code -- although the SystemVerilog standard states "A parameter declaration with no type or range specification shall default to the type and range of the final value assigned to the parameter [...]" (Section 6.20.2 in IEEE 1800-2012).
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another workaround for vivado... well LGTM |
bluewww
approved these changes
Mar 30, 2021
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Please remove the branch once you don't need it anymore |
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Without this explicit type annotation, Vivado 2020.2 fails to synthesize this code -- although the SystemVerilog standard states "A parameter declaration with no type or range specification shall default to the type and range of the final value assigned to the parameter [...]" (Section 6.20.2 in IEEE 1800-2012).