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Enable SVA in Verilator #200
Enable SVA in Verilator #200
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Ping @niwis ⏰ 🙃 |
Thanks a lot, @michael-platzer! I had a chat with @bluewww, and perhaps it would make sense to keep the ability to turn off assertions without doing so (at least per default) for verilator. This would imply replacing I agree that the |
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Thanks @niwis for the feedback, I have replaced the Please let me know if you are happy with the changes. |
I think its better if we name the macro |
@michael-platzer sorry for the back and forth, but could you rename the macro accordingly? Then we can merge this |
No worries 🙂 Macro is renamed. |
Thanks a lot! Could you fix the exceeding line lengths for linting to pass? |
Done, CI looks good now. |
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Awesome, thanks a lot!
This PR removes the
ifndef .. endif
blocks that exclude the assertions from Verilator simulation, thus enabling them in Verilator as well. Hence, the PR fixes #199. As explained in that issue, Verilator has had support for assert properties since at least version 3.922 released in 2018 and support for the implication operator has been added in version 4.026 released in 2020.Three files use a default disable (e.g.,
default disable iff !rst_ni;
), which is not supported by Verilator. The default disable has been left in place, but additionally a disable statement has been added to all assert properties of those files.Note that
stream_xbar
andstream_omega_net
both have the following default disable, which appears to be incorrect:common_cells/src/stream_xbar.sv
Line 169 in 2bd027c
Given the suffix of
rst_ni
, the reset signal appears to be inverted (i.e., low active) and the SVA should probably be disabled ifrst_ni
is low rather than high. I have not modified the default disable for these files but the individual disable statements for each assert property disable the assertion ifrst_ni
is low instead. Please let me know whether this default is intended behavior or whether this should be fixed.All modified files lint successfully in Verilator 5.002.