Override default disable and enable SVA in Verilator for stream_omega…

…_net
pulp-platform · Oct 19, 2023 · a381b59 · a381b59
1 parent efdc531
commit a381b59
Showing 1 changed file with 8 additions and 8 deletions.
diff --git a/src/stream_omega_net.sv b/src/stream_omega_net.sv
@@ -263,26 +263,27 @@ module stream_omega_net #(
     // pragma translate_off
     `ifndef ASSERTS_OFF
     default disable iff rst_ni;
+    `endif
     for (genvar i = 0; unsigned'(i) < NumInp; i++) begin : gen_sel_assertions
-      assert property (@(posedge clk_i) (valid_i[i] |-> sel_i[i] < sel_oup_t'(NumOut))) else
+      assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_i[i] |-> sel_i[i] < sel_oup_t'(NumOut))) else
           $fatal(1, "Non-existing output is selected!");
     end
 
     if (AxiVldRdy) begin : gen_handshake_assertions
       for (genvar i = 0; unsigned'(i) < NumInp; i++) begin : gen_inp_assertions
-        assert property (@(posedge clk_i) (valid_i[i] && !ready_o[i] |=> $stable(data_i[i]))) else
+        assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_i[i] && !ready_o[i] |=> $stable(data_i[i]))) else
             $error("data_i is unstable at input: %0d", i);
-        assert property (@(posedge clk_i) (valid_i[i] && !ready_o[i] |=> $stable(sel_i[i]))) else
+        assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_i[i] && !ready_o[i] |=> $stable(sel_i[i]))) else
             $error("sel_i is unstable at input: %0d", i);
-        assert property (@(posedge clk_i) (valid_i[i] && !ready_o[i] |=> valid_i[i])) else
+        assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_i[i] && !ready_o[i] |=> valid_i[i])) else
             $error("valid_i at input %0d has been taken away without a ready.", i);
       end
       for (genvar i = 0; unsigned'(i) < NumOut; i++) begin : gen_out_assertions
-        assert property (@(posedge clk_i) (valid_o[i] && !ready_i[i] |=> $stable(data_o[i]))) else
+        assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_o[i] && !ready_i[i] |=> $stable(data_o[i]))) else
             $error("data_o is unstable at output: %0d Check that parameter LockIn is set.", i);
-        assert property (@(posedge clk_i) (valid_o[i] && !ready_i[i] |=> $stable(idx_o[i]))) else
+        assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_o[i] && !ready_i[i] |=> $stable(idx_o[i]))) else
             $error("idx_o is unstable at output: %0d Check that parameter LockIn is set.", i);
-        assert property (@(posedge clk_i) (valid_o[i] && !ready_i[i] |=> valid_o[i])) else
+        assert property (@(posedge clk_i) disable iff (~rst_ni) (valid_o[i] && !ready_i[i] |=> valid_o[i])) else
             $error("valid_o at output %0d has been taken away without a ready.", i);
       end
     end
@@ -295,7 +296,6 @@ module stream_omega_net #(
       assert ($clog2(NumLanes) % SelW == 0) else
           $fatal(1, "Bit slicing of the internal selection signal is broken.");
     end
-    `endif
     // pragma translate_on
   end
 endmodule