Design and implantation of an FPGA based 4 channel Logic analyzer on the ALTERA Cyclone IV EP4CE FPGA, integrating ALTERA’s IPs and M9K BRAMs and outputting the analyzed data to a VGA

monitor via a designed VGA interface on the XGA mode The design contains 3 blocks that are

• VGA interface to interface with a VGA monitor on the resolution 1024 x 768
• 4 M9K blocks in the data path for acquiring the sampled data and outputting the data on the monitor
• ALTERA PLL for generating the sampling frequencies 250KHz,1MHz,25MHz,50MHz,the design can captures up to 32K samples for single channel

you can use the .sof file to program your FPGA with intel FPGA programmer tool

The design is seprated into 3 folder Data_Path , Logic_analyzler_ctrl , VGA_Interface, containig the following files :

in the VGA _Interface folder :

• H_SYNC : for generating the horizontal sync pulse of the VGA interface
• V_SYNC : for generating the vertical sync pulse of the VGA interface
• dispaly_FSM : this module reads the sampled data from the memory and controls the Green and blue pins of the interface
• VGA_interface wraps the previous files and adds a controller for the R pin

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in the Data_path folder:

• single_port_ram : contains 4 M9K blocks that writes the sampled data either sequentially or concurrently depending on the number of operating channels.
• write_organzier : controls the writing of the 4 M9K blocks depending on the number of channels
• read_organzier : controls the reading of the sampled data from the 4 M9K blocks
• edge_det : edge detector for rising and falling edges works as a trigger, channel 1 is the one triggering the whole system it should always be used for the triggering signal
• RA_CTRL: controls zooming and offset of the display
• glitch_free_clock_mux : used to multiplex the sampling clock and the main 65 MHz clock as the memory is written with sampling clock and read with sampling clock use the ALTERA PLL IP for genrating diffrent sampling frequnicies and multiplex them using a regualar multiplixer no problem

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in the logic_analyzer_ctrl folder:

• Debounce_filter : used to debounce the evalution board switches
• zoom_ctrl, offset_Ctrl and smpl_clk_control used to control dispaly offset, zooming and choosing the sample clock

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Pin assigmnets:

the design needs 6 switches for 1 for channel mode (mode), 2 for zoom, 2 for offset and 1 for sample clock select I only had 5 also you will need to use a jumper wire for reset and start pins.

• sample_clock_sel switch controls the LEDs you have 4 sampling frequnices indicated by the 4 LEDs
• reset pin is active high make sure it's grounded when not in use
• datain [3:0] are the data input pins of every channel data[0] is the triggring channel that triggers the whole system
• start pin is used to start sampling if the pin is high level if not datain[0] data won't trigger the system

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