firtool-1.78.0

What's Changed

• [CI] Drop macos-11 runners, use macos-12 in uploadReleaseArtifacts by @jackkoenig in #7319
• [llvm] Bump to 0870afaaaccde5b4bae37abfc982207ffafb8332 by @leonardt in #7318
• [MooreToCore] Lower var, read, and assign into LLHD. by @hailongSun2000 in #7297
• [circt-bmc] Add ExternaliseRegisters Pass by @TaoBi22 in #7285
• [Sim] Flatten format string concatenations in canonicalizer by @fzi-hielscher in #7316
• Reland "[FIRRTL][LowerClass] Pre-allocate namespaces before capturing refs (#7102)". by @mikeurbach in #7328
• [Sim] Add printing operations and transformation from non-procedural to procedural flavor by @fzi-hielscher in #7292
• [PyCDE] Simple transforms on channels by @teqdruid in #7330
• [PyCDE] Bundles: coerce method by @teqdruid in #7331
• [ExportVerilog] Add "context" to imported DPI functions by @uenoku in #7333
• [ImportVerilog] Fix unbased unsized literals of packed aggregate type by @fabianschuiki in #7336
• [Verif] Add formal test intent ops by @dobios in #7145
• [ImportVerilog]Dedup module Op by @mingzheTerapines in #7245
• [ImportVerilog] Accept empty packages by @fabianschuiki in #7334
• [ImportVerilog] [SROA] [Mem2Reg][Canonicalizers]Support Passes for Nested Type by @mingzheTerapines in #7158
• [ESI Runtime] Windows: python support and backend plugin loading by @teqdruid in #7338
• [SV] Add UnpackedArrayCreateOp by @uenoku in #7303
• [ImportVerilog] Handle $signed/$unsigned system tasks by @fabianschuiki in #7337
• [FIRRTL][FIRParser] Tokenize Commas by @mmaloney-sf in #7206
• [ImportVerilog] Allow enum variants in expressions by @fabianschuiki in #7339
• [MooreToCore] Support NegOp lowering by @maerhart in #7344
• [FIRRTL] AssignOutputDirs: Ensure absolute dirs end with trailing slash by @rwy7 in #7348

Full Changelog: firtool-1.77.0...firtool-1.78.0