[CheckCombLoops] Handle RWProbeOp

[prithayan]

Handle the RWProbeOp in CheckCombLoop.
This fixes #6820

[dtzSiFive]

Thanks!! Glad this generally doesn't look like a big change.

Unsure of some things, gotta run but will circle back.

Please take a look at the examples posted.

[dtzSiFive]

Having hard time getting GitHub to let me "suggest" this properly, but this comment, line, before, and if/return can now be deleted.

[dtzSiFive]

Let's make this a utility (this is from InferWidths looks like, hopefully it is).

Not blocking but if not addressed please file an issue and assign to me.

[dtzSiFive]

Does this work if the rwprobe target isn't a leaf (multiple FieldRef's)?

(not sure how this works, but do we create edge for all fields connected?)

[dtzSiFive]

Consider:

FIRRTL version 3.3.0
circuit Bar :
  module Foo :
    input agg : { x: Clock, y : Clock }
    output ref : RWProbe<{ x: Clock, y : Clock }>
    output refx : RWProbe<Clock>

    define ref = rwprobe(agg)
    define refx = rwprobe(agg.x)

  module Bar :
    input clock : Clock

    inst foo of Foo
    connect foo.agg.x, clock
    connect foo.agg.y, clock

    force(clock, UInt<1>(1), foo.ref.x, read(foo.refx))

Which should report a cycle but doesn't.

[dtzSiFive]

I believe you but if you could spare a word for what this does/why that'd be swell. Thank you!

If there's a path from a non-probe to a rwprobe, record a probe edge sink -> source? I'm not sure that's right, consider:

FIRRTL version 3.3.0
circuit Bar :
  module Foo :
    input clock : Clock
    output out : Clock
    output clockProbe_bore : RWProbe<Clock>

    node n = clock

    define clockProbe_bore = rwprobe(n)
    connect out, clock

  module Bar :
    input clock : Clock
    output clockProbe : RWProbe<Clock>

    inst foo of Foo
    connect foo.clock, clock
    define clockProbe = foo.clockProbe_bore

    force(clock, UInt<1>(1), clockProbe, foo.out)

Which reports a cycle but there isn't one, forcing n is unused.

[prithayan]

Thanks for spotting this, I need to fix the logic to track which ports can be updated by a probe. Working on it.