Commits on Dec 7, 2023

1. [firtool] Add option to treat EICG_wrapper as intrinsic …

   Add the `--fixup-eicg-wrapper` option to firtool and the LowerIntrinsics
   pass. Setting the option will treat `EICG_wrapper` modules like an
   intrinsic and replace them with the `firrtl.int.clock_gate` operation.
   
   In the long run, Chisel/FIRRTL designs will directly emit the clock gate
   intrinsic, and `EICG_wrapper` extmodules will be gone. However until we
   get there, this option provides an incremental path towards deprecating
   the `EICG_wrapper` pattern. It allows us to switch the CIRCT side of the
   flow over to the intrinsic without having to make changes to Chisel in
   lockstep. Once all relevant existing designs work with this switch
   enabled, Chisel projects can opt into emitting clock gates directly, and
   can gradually upgrade. At that point we can make firtool emit
   deprecation warnings for uses of `EICG_wrapper` extmodules, and at some
   point we can entirely drop special handling of these modules altogether.
   
   This switch is disabled by default and does not affect existing flows.

   

   fabianschuiki committed Dec 7, 2023
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