[FIRRTL] Fix unpacked array ordering in GCT and ExportVerilog #2049
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The FIRRTL Grand Central pass and ExportVerilog currently order unpacked arrays in reverse upon emission. A nested array like `uarray<2 x uarray<3 x i1>>` has the shape `[[a,b,c], [d,e,f]]` and should produce the following verilog: logic foo [2][3]; // non-range indices used for clarity Generally the following SV declaration: logic [2:0][1:0] bar [4:0][3:0]; Reads its dimensions from outer- to innermost as: [4:0], [3:0], [2:0], [1:0] Currently, ExportVerilog will emit the above `foo` example as `foo[3][2]`, which is incorrect. Fixing ExportVerilog also provides a fix for an issue @seldridge tackled earlier in ca5bfac. This change reverts parts of that older fix since the updated declaration order now makes the original Grand Central index order correct. The output now matches what the Scala FIRRTL compiler produces.
fabianschuiki
added
FIRRTL
seldridge
approved these changes
Oct 28, 2021
| @@ -54,7 +54,7 @@ struct VerbatimType { | |||
| SmallString<64> stringType(str); | |||
| stringType.append(" "); | |||
| stringType.append(name); | |||
| for (auto d : dimensions) { | |||
| for (auto d : llvm::reverse(dimensions)) { | |||
|
Awesome, thanks for hitting merge on this! |
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The FIRRTL Grand Central pass and ExportVerilog currently order unpacked arrays in reverse upon emission. A nested array like
uarray<2 x uarray<3 x i1>>has the shape[[a,b,c], [d,e,f]]and should produce the following verilog:Generally the following SV declaration:
Reads its dimensions from outer- to innermost as:
Currently, ExportVerilog will emit the above
fooexample asfoo[3][2], which is incorrect. Fixing ExportVerilog also provides a fix for an issue @seldridge tackled earlier in ca5bfac. This change reverts parts of that older fix since the updated declaration order now makes the original Grand Central index order correct.The output now matches what the Scala FIRRTL compiler produces.