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Issues list

[ExportVerilog] Pass should fail if any failure occurs while running ExportVerilog
#7484 opened Aug 9, 2024 by teqdruid
3
[ExportVerilog] Should ignore unknown top-level ops ExportVerilog
#6426 opened Nov 17, 2023 by teqdruid
4
How to remove _GEN wires? ExportVerilog
#5541 opened Jul 6, 2023 by flexiot
2
[ExportVerilog] Clean up FlatSymbolRefAttr emission ExportVerilog good first issue Good for newcomers
#5217 opened May 17, 2023 by uenoku
[ExportVerilog] Drop alignment, explore pretty-printing types/structs. (draft/experimenting) ExportVerilog
#5189 opened May 12, 2023 by dtzSiFive • Draft
1
[ExportVerilog] disallowPackedStructAssignments also needs to consider hw.aggregate_constant ExportVerilog
#5138 opened May 5, 2023 by mortbopet
[LegalizeNames] Typedecls need to be checked if they collide with reserved words ExportVerilog
#5089 opened Apr 26, 2023 by youngar
[ExportVerilog][SV] sv.interface instance name not Verilog-keyword mangled bug Something isn't working ExportVerilog
#4849 opened Mar 17, 2023 by seldridge
[ExportVerilog][Windows] Split verilog clobbers files with different cases ExportVerilog
#4807 opened Mar 11, 2023 by teqdruid
[ExportVerilog] "$name is not allowed in Verilog output" error does not fail pass bug Something isn't working ExportVerilog
#4770 opened Mar 6, 2023 by dtzSiFive
[ExportVerilog] Add Emission Option for Unique Case-insensitive Names in Module Scope enhancement New feature or request ExportVerilog
#4561 opened Jan 20, 2023 by seldridge
2
[FIRRTL] Excessive DSP slice use on Xilinx FPGAs ExportVerilog FIRRTL Involving the `firrtl` dialect HW Involving the `hw` dialect
#4549 opened Jan 17, 2023 by fabianschuiki
1
ExportVerilog crashes when encountering an seq.firrtlreg ExportVerilog Seq Involving the `seq` dialect
#3966 opened Sep 21, 2022 by darthscsi
2
[ExportVerilog] Initial statement needs begin/end for single declaration bug Something isn't working ExportVerilog
#3454 opened Jun 30, 2022 by uenoku
1
[FIRRTL][Verilog] Use Xcelium Coverage Exclusion Magic in Addition to VCS ExportVerilog FIRRTL Involving the `firrtl` dialect
#3329 opened Jun 11, 2022 by seldridge
3
[ExportVerilog] Smarter handling of large expression splitting and spilling. enhancement New feature or request ExportVerilog
#2810 opened Mar 25, 2022 by mikeurbach
@mikeurbach
[ExportVerilog] Reuse wire/register declarations ExportVerilog Verilog Quality
#2624 opened Feb 14, 2022 by uenoku
2
[ExportVerilog] Omit bitwidth of constant array index ExportVerilog
#2593 opened Feb 7, 2022 by uenoku
2
[ExportVerilog] Unnecessary temporary wire for bitcast between array and integer ExportVerilog
#2590 opened Feb 6, 2022 by uenoku
2
[ExportVerilog] Type scope emission in split outputs mode ExportVerilog
#2583 opened Feb 4, 2022 by uenoku
3
[ExportVerilog] Incorrect verilog output for bitcast + zero width aggregate types bug Something isn't working ExportVerilog
#2504 opened Jan 23, 2022 by uenoku
[ExportVerilog] Consider to cache results of isExpressionUnableToInline ExportVerilog
#2489 opened Jan 21, 2022 by uenoku
2
[ExportVerilog] Remove temporary for aggregate outputs ExportVerilog Verilog Quality
#2439 opened Jan 9, 2022 by uenoku
[LowerToHW] Use type decl for Bundle type lowering enhancement New feature or request ExportVerilog
#2329 opened Dec 12, 2021 by uenoku
1
[ExportVerilog] Add support for bit swapping idiom ExportVerilog
#2249 opened Nov 29, 2021 by lattner
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