[ModuleInliner] Donot retop if flattening the module

llvm · Dec 22, 2023 · bcc1eea · bcc1eea
1 parent ae417df
commit bcc1eea
Show file tree

Hide file tree

Showing 2 changed files with 30 additions and 1 deletion.
diff --git a/lib/Dialect/FIRRTL/Transforms/ModuleInliner.cpp b/lib/Dialect/FIRRTL/Transforms/ModuleInliner.cpp
@@ -1150,7 +1150,7 @@ void Inliner::inlineInstances(FModuleOp module) {
     // participate in any HierPathOp. But the reTop might add a symbol to it, if
     // a HierPathOp is added to this Op.
     DenseMap<Attribute, Attribute> symbolRenames;
-    if (!rootMap[target.getNameAttr()].empty()) {
+    if (!rootMap[target.getNameAttr()].empty() && !shouldFlatten(target)) {
       for (auto sym : rootMap[target.getNameAttr()]) {
         auto &mnla = nlaMap[sym];
         sym = mnla.reTop(module);

diff --git a/test/Dialect/FIRRTL/inliner.mlir b/test/Dialect/FIRRTL/inliner.mlir
@@ -1417,3 +1417,32 @@ firrtl.circuit "PropertyUTurn" {
   }
   firrtl.extmodule @Consume(in in : !firrtl.string)
 }
+
+// -----
+
+// Test that inlining and flattening compose with nla well.
+firrtl.circuit "compose_nla" {
+  hw.hierpath private @nla1 [@test1::@sym, @test2::@sym, @test3]
+// CHECK-NOT:  hw.hierpath private @nla1
+firrtl.module @compose_nla() {
+// CHECK-LABEL: firrtl.module @compose_nla() {
+  firrtl.instance test1 @test1()
+  firrtl.instance test2 @test2()
+  firrtl.instance test3 @test3()
+}
+firrtl.module private @test1() attributes {annotations =
+        [{class = "firrtl.transforms.FlattenAnnotation"},
+         {class = "firrtl.passes.InlineAnnotation"}]} {
+  %test_wire = firrtl.wire : !firrtl.uint<2>
+  firrtl.instance test2 sym @sym @test2()
+  firrtl.instance test3 @test3()
+}
+firrtl.module private @test2() attributes {annotations =
+        [{class = "firrtl.passes.InlineAnnotation"}]} {
+  %test_wire = firrtl.wire : !firrtl.uint<2>
+  firrtl.instance test3 sym @sym @test3()
+}
+firrtl.module private @test3() {
+  %test_wire = firrtl.wire : !firrtl.uint<2>
+}
+}