Walk over nested regions

llvm · Oct 25, 2023 · 1004c57 · 1004c57
1 parent 1987f3b
commit 1004c57
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Showing 2 changed files with 27 additions and 3 deletions.
diff --git a/lib/Dialect/FIRRTL/Transforms/Lint.cpp b/lib/Dialect/FIRRTL/Transforms/Lint.cpp
@@ -18,9 +18,17 @@ namespace {
 struct LintPass : public LintBase<LintPass> {
   void runOnOperation() override {
     auto fModule = getOperation();
-    for (auto &op : fModule.getOps())
-      if (checkAssert(&op).failed())
-        return signalPassFailure();
+    auto walkResult = fModule.walk<WalkOrder::PreOrder>([&](Operation *op) {
+      if (isa<WhenOp>(op))
+        return WalkResult::skip();
+      if (isa<AssertOp, VerifAssertIntrinsicOp>(op))
+        if (checkAssert(op).failed())
+          return WalkResult::interrupt();
+
+      return WalkResult::advance();
+    });
+    if (walkResult.wasInterrupted())
+      return signalPassFailure();
 
     markAllAnalysesPreserved();
   };

diff --git a/test/Dialect/FIRRTL/lint.mlir b/test/Dialect/FIRRTL/lint.mlir
@@ -13,6 +13,10 @@ firrtl.circuit "lint_tests" {
     firrtl.assert %clock, %false, %en, "valid" : !firrtl.clock, !firrtl.uint<1>, !firrtl.uint<1>  {eventControl = 0 : i32, isConcurrent = false}
     // CHECK: firrtl.int.verif.assert
     firrtl.int.verif.assert %pred : !firrtl.uint<1>
+    // CHECK: firrtl.int.verif.assert
+    firrtl.when %en : !firrtl.uint<1> {
+      firrtl.int.verif.assert %false : !firrtl.uint<1>
+    }
   }
 }
 
@@ -63,4 +67,16 @@ firrtl.circuit "assert_reset2" {
   }
 }
 
+// -----
 
+firrtl.circuit "assert_reset3" {
+firrtl.declgroup @GroupFoo bind {}
+  // expected-note @below {{reset signal defined here}}
+  firrtl.module @assert_reset3(in %en: !firrtl.uint<1>, in %pred: !firrtl.uint<1>, in %reset: !firrtl.reset, in %reset_async: !firrtl.asyncreset, in %clock: !firrtl.clock) {
+    %0 = firrtl.asUInt %reset : (!firrtl.reset) -> !firrtl.uint<1>
+    firrtl.group @GroupFoo {
+      // expected-error @below {{op is guaranteed to fail simulation, as the predicate is a reset signal}}
+      firrtl.int.verif.assert %0 : !firrtl.uint<1>
+    }
+  }
+}