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CUGR, VLSI Global Routing Tool Developed by CUHK

C++ 118 40 Updated Feb 27, 2023

A maze router

C++ 4 4 Updated Feb 19, 2017

Exercises for exploring the Fibertree, Timeloop and Accelergy tools

Jupyter Notebook 80 28 Updated Sep 5, 2024
Jupyter Notebook 38 9 Updated Sep 8, 2024

Command-line design environment for asynchronous logic

C++ 6 Updated Aug 7, 2024

Simulator for ACT hardware description language

C++ 8 7 Updated Sep 29, 2024

This MATLAB and Simulink Challenge Project Hub contains a list of research and design project ideas. These projects will help you gain practical experience and insight into technology trends and in…

MATLAB 1,235 270 Updated Sep 13, 2024

Design and Validation of a Customizable 50th-Order Low-Pass FIR Filter. Transitioning from MATLAB Modeling to Verilog RTL Design and simulation Testing.

Verilog 4 Updated May 11, 2024

Verilog Codes for Quadcopter Project

Verilog 1 Updated Jan 30, 2022

Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.

Verilog 137 29 Updated Mar 26, 2022
Python 1 Updated Jan 8, 2023

Model SAR ADC with python!

Jupyter Notebook 18 7 Updated Jul 8, 2022

CrossSim: accuracy simulation of analog in-memory computing

Jupyter Notebook 116 26 Updated Sep 24, 2024

LunaPnR is a place and router for integrated circuits

Verilog 40 1 Updated Jul 25, 2024

LMS Adaptive Filter implementation using Vedic Multiplication and Manchester Carry Chain ADder

Verilog 3 Updated Oct 27, 2023

Reset and CDC synchronizers developed in Verilog/System Verilog.

SystemVerilog 3 1 Updated Dec 8, 2023

basic synchronizers used in CDC paths ( Verilog)

Verilog 3 Updated Jul 20, 2023

Verilog evaluation benchmark for large language model

SystemVerilog 161 22 Updated Aug 21, 2024

Running Python code in SystemVerilog

Python 61 12 Updated Jul 22, 2024

Parametric layout generator for digital, analog and mixed-signal integrated circuits

C 48 6 Updated Jul 17, 2024

GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called pr…

C++ 195 32 Updated Aug 20, 2024

Reads a Cadence techfile into KLayout and produces layer properties from it

Ruby 23 5 Updated Oct 22, 2023

😎 curated list of open source photonics projects

Makefile 324 43 Updated Sep 25, 2024

130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design

HTML 381 59 Updated Sep 30, 2024

Hdl21 Schematics

TypeScript 1 Updated Jan 22, 2023

Parsing and generating popular formats of circuit netlist

Python 28 1 Updated Dec 10, 2022

This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.

20 7 Updated Feb 21, 2019

a graphical tool to visualize binary data

Rust 1,088 31 Updated May 5, 2024

FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation

VHDL 81 18 Updated May 11, 2023

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

SystemVerilog 783 89 Updated Jun 21, 2024
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