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Exercises for exploring the Fibertree, Timeloop and Accelergy tools
Command-line design environment for asynchronous logic
This MATLAB and Simulink Challenge Project Hub contains a list of research and design project ideas. These projects will help you gain practical experience and insight into technology trends and in…
Design and Validation of a Customizable 50th-Order Low-Pass FIR Filter. Transitioning from MATLAB Modeling to Verilog RTL Design and simulation Testing.
Verilog Codes for Quadcopter Project
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
CrossSim: accuracy simulation of analog in-memory computing
LunaPnR is a place and router for integrated circuits
LMS Adaptive Filter implementation using Vedic Multiplication and Manchester Carry Chain ADder
Reset and CDC synchronizers developed in Verilog/System Verilog.
basic synchronizers used in CDC paths ( Verilog)
Verilog evaluation benchmark for large language model
Parametric layout generator for digital, analog and mixed-signal integrated circuits
GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called pr…
Reads a Cadence techfile into KLayout and produces layer properties from it
😎 curated list of open source photonics projects
130nm BiCMOS Open Source PDK, dedicated for Analog, Mixed Signal and RF Design
ThomasPluck / Hdl21Schematics
Forked from Vlsir/Hdl21SchematicsHdl21 Schematics
Parsing and generating popular formats of circuit netlist
This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.
FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation
OpenSource GPU, in Verilog, loosely based on RISC-V ISA