basic synchronizers used in CDC paths ( Verilog)
If the setup and hold time requirements are not met, the output of the flipflop may take much longer than Tco to a valid logic. This is called unstable behavior or metastability
The metastability occurrences can be predicted by using the mean time between failures (MTBF) formula:
Where C1 and C2 are constants that depend on the technology used to build the flip-flop; tMET is the duration of the metastable output; and fclk and fdata are the frequencies of the synchronous clock and the asynchronous input, respectively.
instead of using a flop synchronizer for each flipflop, we can use a single flop synchronizer for each flipflop. We can use a single flop synchronizer to control the path for multi-bit data and that can be controlled by a mux
there may be some bits in the previous value and some are in the new value, to avoid these functional errors we use gray encoding (only one-bit changes at a time )
Request signal synchronous with receiving clock domain and recognized correctly at receiving end.
After data is captured correctly the destination end sends an acknowledgment signal to the transmitting domain end.
Fast to slow clock domain (chances of missing pulse). converting pulse to level.
Back-to-back pulses can't be handled in pulse synchronizers. If more than one pulse comes handshake-based pulse synchronizer is used.
Full and Empty signals can be generated by comparing the read and write pointers of the FIFO. However, both the read and the write pointers are operating at asynchronous clocks. Hence, comparing them directly could result in failure, due to Clock Domain Crossing.
The Empty signal is used to control the read side of the circuitry. Thus, for gener�ating the Empty signal, you should synchronize the write pointer to the read clock. Similarly, for generating the Full signal, you should synchronize the read pointer to the write clock. Since the read and write pointers are both address busses, and they both are going to be synchronized to write and read clocks respectively, so, you should use grey-counters to generate read and write pointers.
It is worth noting that a FIFO would be Full only at the update of a write pointer. However, it would come out of the Full only at the update of a read pointer. The schematic shows that for the generation of Full signal, the write pointer feeds in directly to the comparator. That means, the generation of the Full signal is without any delay. However, due to the delay (because of synchronization) on the read pointer side, the FIFO might take an extra cycle to deassert the Full signal. Similarly, for the generation of Empty signal, the read pointer feeds in directly to the comparator. That means, the generation of the Empty signal is without any delay. However, due to the delay on the write pointer side, the FIFO might take an extra cycle to deassert the Empty signal.
So, effectively, the assertion of Full and Empty happens without any delay. But, the deassertion might involve an extra cycle. This means, there might be an additional wasted cycle; however, this additional wasted cycle is worth it – to prevent any failure.