[RISC-V] Synthesizing PC-relative pointer constants #119203

tomeksowi · 2025-08-29T11:32:46Z

RISC-V is ill-equipped to synthesize large >32-bit constants like absolute pointers, it results in a 6-8 instruction sequence. If an address can be synthesized as PC-relative (2 instructions: auipc + ld/addi), do so. It also simplifies codegen.

Part of #84834, cc @dotnet/samsung

dotnet-policy-service · 2025-08-29T11:33:47Z

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

tomeksowi · 2025-09-01T15:36:38Z

@risc-vv /run

risc-vv · 2025-09-01T15:41:28Z

RISC-V pull_request-CLR-QEMU: 9108 / 9139 (99.66%)

=======================
      passed: 9108
      failed: 3
     skipped: 586
      killed: 28
------------------------
 TOTAL tests: 9725
VIRTUAL time: 80h 13min 42s 134ms
   REAL time: 1h 18min 35s 828ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V pull_request-CLR-VF2: 9108 / 9139 (99.66%)

=======================
      passed: 9108
      failed: 3
     skipped: 586
      killed: 28
------------------------
 TOTAL tests: 9725
VIRTUAL time: 32h 6min 37s 777ms
   REAL time: 2h 7min 32s 224ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V pull_request-FX-QEMU: 0 / 0 (100.00%)

=======================
      passed: 0
      failed: 0
     skipped: 14
      killed: 0
------------------------
 TOTAL tests: 14
VIRTUAL time: 0ms
   REAL time: 4h 30min 0s 477ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

RISC-V pull_request-FX-VF2: 0 / 61 (0.00%)

=======================
      passed: 0
      failed: 0
     skipped: 14
      killed: 61
------------------------
 TOTAL tests: 75
VIRTUAL time: 1min 14s 744ms
   REAL time: 13h 0min 6s 48ms
=======================

report.xml, report.md, failures.xml, testclr_details.tar.zst

Build information and commands

GIT: bd0e79cc0470c7eae53ef67028e7c567c9fb9846
CI: 0dd2da79b21e6d27378407c3af1305973fd300aa
REPO: dotnet/runtime
BRANCH: main
CONFIG: Checked
LIB_CONFIG: Release

tomeksowi · 2025-09-01T15:50:12Z

No regressions. Quite a bit of post-bringup cruft went out the window.

Diffs are based on 104,367 contexts (2,270 MinOpts, 102,097 FullOpts).

MISSED contexts: 2 (0.00%)

Overall (-9,469,872 bytes)

Collection	Base size (bytes)	Diff size (bytes)	PerfScore in Diffs
linux.riscv64.Checked.3.mch	71,889,656	-9,469,872	-7.46%

MinOpts (-2,342,108 bytes)

Collection	Base size (bytes)	Diff size (bytes)	PerfScore in Diffs
linux.riscv64.Checked.3.mch	16,685,964	-2,342,108	-7.73%

FullOpts (-7,127,764 bytes)

Collection	Base size (bytes)	Diff size (bytes)	PerfScore in Diffs
linux.riscv64.Checked.3.mch	55,203,692	-7,127,764	-7.45%

Example diffs

linux.riscv64.Checked.3.mch

-48 (-41.38%) : 53568.dasm - Program:Main():int (FullOpts)

@@ -20,35 +20,23 @@ G_M24375_IG01:        ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref,
             mv             fp, sp
 						;; size=16 bbWeight=1 PerfScore 9.00
 G_M24375_IG02:        ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref
-            lui            t6, 0xD1FFAB1E
-            addiw          t6, t6, 0xD1FFAB1E
-            slli           t6, t6, 13
-            addi           t6, t6, 0xD1FFAB1E
-            slli           t6, t6, 2
-            ld             a0, 0xD1FFAB1E(t6)
+            auipc          a0, 0xD1FFAB1E
+            ld             a0, 0xD1FFAB1E(a0)
             jalr           a0		// <unknown method>
-            lui            t6, 0xD1FFAB1E
-            addiw          t6, t6, 0xD1FFAB1E
-            slli           t6, t6, 13
-            addi           t6, t6, 0xD1FFAB1E
-            slli           t6, t6, 2
-            ld             a0, 0xD1FFAB1E(t6)
+            auipc          a0, 0xD1FFAB1E
+            ld             a0, 0xD1FFAB1E(a0)
             jalr           a0		// <unknown method>
-            lui            t6, 0xD1FFAB1E
-            addiw          t6, t6, 0xD1FFAB1E
-            slli           t6, t6, 13
-            addi           t6, t6, 0xD1FFAB1E
-            slli           t6, t6, 2
-            ld             a0, 0xD1FFAB1E(t6)
+            auipc          a0, 0xD1FFAB1E
+            ld             a0, 0xD1FFAB1E(a0)
             jalr           a0		// Test:Ret():int
-						;; size=84 bbWeight=1 PerfScore 30.00
+						;; size=36 bbWeight=1 PerfScore 15.00
 G_M24375_IG03:        ; bbWeight=1, epilog, nogc, extend
             ld             ra, 8(sp)
             ld             fp, 0(sp)
             addi           sp, sp, 16
             ret						;; size=16 bbWeight=1 PerfScore 7.50
 
-; Total bytes of code 116, prolog size 16, PerfScore 46.50, instruction count 17, allocated bytes for code 116 (MethodHash=d9b8a0c8) for method Program:Main():int (FullOpts)
+; Total bytes of code 68, prolog size 16, PerfScore 31.50, instruction count 14, allocated bytes for code 68 (MethodHash=d9b8a0c8) for method Program:Main():int (FullOpts)
 ; ============================================================
 
 Unwind Info:
@@ -59,7 +47,7 @@ Unwind Info:
   E bit             : 0
   X bit             : 0
   Vers              : 0
-  Function Length   : 58 (0x0003a) Actual length = 116 (0x000074)
+  Function Length   : 34 (0x00022) Actual length = 68 (0x000044)
   ---- Epilog scopes ----
   ---- Scope 0
   Epilog Start Offset        : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)

-32 (-40.00%) : 54962.dasm - ExceptionExtensions:RethrowWithNoStackTraceLoss(System.Exception) (FullOpts)

@@ -21,26 +21,18 @@ G_M64910_IG01:        ; bbWeight=0, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref,
 						;; size=16 bbWeight=0 PerfScore 0.00
 G_M64910_IG02:        ; bbWeight=0, gcrefRegs=0400 {a0}, byrefRegs=0000 {}, byref
             ; gcrRegs +[a0]
-            lui            t6, 0xD1FFAB1E
-            addiw          t6, t6, 0xD1FFAB1E
-            slli           t6, t6, 12
-            addi           t6, t6, 0xD1FFAB1E
-            slli           t6, t6, 3
-            ld             a1, 0xD1FFAB1E(t6)
+            auipc          a1, 0xD1FFAB1E
+            ld             a1, 0xD1FFAB1E(a1)
             jalr           a1		// System.Runtime.ExceptionServices.ExceptionDispatchInfo:Capture(System.Exception):System.Runtime.ExceptionServices.ExceptionDispatchInfo
-            lui            t6, 0xD1FFAB1E
-            addiw          t6, t6, 0xD1FFAB1E
-            slli           t6, t6, 12
-            addi           t6, t6, 0xD1FFAB1E
-            slli           t6, t6, 3
-            ld             a1, 0xD1FFAB1E(t6)
+            auipc          a1, 0xD1FFAB1E
+            ld             a1, 0xD1FFAB1E(a1)
             lw             zero, 0xD1FFAB1E(a0)
             jalr           a1		// System.Runtime.ExceptionServices.ExceptionDispatchInfo:Throw():this
             ; gcrRegs -[a0]
             ebreak
-						;; size=64 bbWeight=0 PerfScore 0.00
+						;; size=32 bbWeight=0 PerfScore 0.00
 
-; Total bytes of code 80, prolog size 16, PerfScore 0.00, instruction count 12, allocated bytes for code 80 (MethodHash=95e60271) for method ExceptionExtensions:RethrowWithNoStackTraceLoss(System.Exception) (FullOpts)
+; Total bytes of code 48, prolog size 16, PerfScore 0.00, instruction count 10, allocated bytes for code 48 (MethodHash=95e60271) for method ExceptionExtensions:RethrowWithNoStackTraceLoss(System.Exception) (FullOpts)
 ; ============================================================
 
 Unwind Info:
@@ -51,7 +43,7 @@ Unwind Info:
   E bit             : 0
   X bit             : 0
   Vers              : 0
-  Function Length   : 40 (0x00028) Actual length = 80 (0x000050)
+  Function Length   : 24 (0x00018) Actual length = 48 (0x000030)
   ---- Epilog scopes ----
   No epilogs
   ---- Unwind codes ----

-40 (-38.46%) : 856.dasm - Interop:g__ParentDirectoryExists|7_0(System.String):bool (FullOpts)

@@ -22,25 +22,15 @@ G_M36700_IG01:        ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref,
 						;; size=16 bbWeight=1 PerfScore 9.00
 G_M36700_IG02:        ; bbWeight=1, gcrefRegs=0400 {a0}, byrefRegs=0000 {}, byref
             ; gcrRegs +[a0]
-            lui            t6, 0xD1FFAB1E
-            addiw          t6, t6, 0xD1FFAB1E
-            slli           t6, t6, 13
-            addi           t6, t6, 0xD1FFAB1E
-            slli           t6, t6, 2
-            ld             a1, 0xD1FFAB1E(t6)
+            auipc          a1, 0xD1FFAB1E
+            ld             a1, 0xD1FFAB1E(a1)
             jalr           a1		// System.IO.PathInternal:TrimEndingDirectorySeparator(System.String):System.String
-            lui            t6, 0xD1FFAB1E
-            addiw          t6, t6, 0xD1FFAB1E
-            slli           t6, t6, 32
-            srli           t6, t6, 18
-            ld             a1, 0xD1FFAB1E(t6)
+            auipc          a1, 0xD1FFAB1E
+            ld             a1, 0xD1FFAB1E(a1)
             jalr           a1		// System.IO.Path:GetDirectoryName(System.String):System.String
-            lui            t6, 0xD1FFAB1E
-            addiw          t6, t6, 0xD1FFAB1E
-            slli           t6, t6, 32
-            srli           t6, t6, 18
-            ld             a1, 0xD1FFAB1E(t6)
-						;; size=72 bbWeight=1 PerfScore 25.00
+            auipc          a1, 0xD1FFAB1E
+            ld             a1, 0xD1FFAB1E(a1)
+						;; size=32 bbWeight=1 PerfScore 12.00
 G_M36700_IG03:        ; bbWeight=1, epilog, nogc, extend
             ld             ra, 8(sp)
             ld             fp, 0(sp)
@@ -48,7 +38,7 @@ G_M36700_IG03:        ; bbWeight=1, epilog, nogc, extend
             jr             a1		// System.IO.Directory:Exists(System.String):bool
 						;; size=16 bbWeight=1 PerfScore 7.50
 
-; Total bytes of code 104, prolog size 16, PerfScore 41.50, instruction count 16, allocated bytes for code 104 (MethodHash=027470a3) for method Interop:<GetExceptionForIoErrno>g__ParentDirectoryExists|7_0(System.String):bool (FullOpts)
+; Total bytes of code 64, prolog size 16, PerfScore 28.50, instruction count 13, allocated bytes for code 64 (MethodHash=027470a3) for method Interop:<GetExceptionForIoErrno>g__ParentDirectoryExists|7_0(System.String):bool (FullOpts)
 ; ============================================================
 
 Unwind Info:
@@ -59,7 +49,7 @@ Unwind Info:
   E bit             : 0
   X bit             : 0
   Vers              : 0
-  Function Length   : 52 (0x00034) Actual length = 104 (0x000068)
+  Function Length   : 32 (0x00020) Actual length = 64 (0x000040)
   ---- Epilog scopes ----
   ---- Scope 0
   Epilog Start Offset        : 3523193630 (0xd1ffab1e) Actual offset = 3523193630 (0xd1ffab1e) Offset from main function begin = 3523193630 (0xd1ffab1e)

+0 (0.00%) : 104032.dasm - Microsoft.Diagnostics.Tracing.TraceEvent:get_FormattedMessage():System.String:this (FullOpts)

@@ -22,6 +22,7 @@ G_M51530_IG01:        ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref,
 G_M51530_IG02:        ; bbWeight=1, gcrefRegs=0400 {a0}, byrefRegs=0000 {}, byref
             ; gcrRegs +[a0]
             mv             a1, zero
+            ; gcrRegs +[a1]
             ld             a2, 0xD1FFAB1E(a0)
             ld             a2, 0xD1FFAB1E(a2)
             ld             a2, 0xD1FFAB1E(a2)

+0 (0.00%) : 57024.dasm - UDivConst:U8_Div_3(ulong):ulong (FullOpts)

No diffs found?

+0 (0.00%) : 56976.dasm - SlowPathELTTests.SlowPathELTHelpers:MixedSseStructFunc():SlowPathELTTests.MixedSseStruct (FullOpts)

No diffs found?

Details

Size improvements/regressions per collection

Collection	Contexts with diffs	Improvements	Regressions	Same size	Improvements (bytes)	Regressions (bytes)
linux.riscv64.Checked.3.mch	78,139	76,854	0	1,285	-9,469,872	+0

PerfScore improvements/regressions per collection

Collection	Contexts with diffs	Improvements	Regressions	Same PerfScore	Improvements (PerfScore)	Regressions (PerfScore)	PerfScore Overall in FullOpts
linux.riscv64.Checked.3.mch	78,139	57,537	0	20,602	-9.99%	0.00%	-5.6031%

Context information

Collection	Diffed contexts	MinOpts	FullOpts	Missed, base	Missed, diff
linux.riscv64.Checked.3.mch	104,367	2,270	102,097	2 (0.00%)	2 (0.00%)

jit-analyze output

tomeksowi · 2025-09-01T16:12:03Z

+0 (0.00%) : 104032.dasm - Microsoft.Diagnostics.Tracing.TraceEvent:get_FormattedMessage():System.String:this (FullOpts)

@@ -22,6 +22,7 @@ G_M51530_IG01:        ; bbWeight=1, gcrefRegs=0000 {}, byrefRegs=0000 {}, byref,
 G_M51530_IG02:        ; bbWeight=1, gcrefRegs=0400 {a0}, byrefRegs=0000 {}, byref
             ; gcrRegs +[a0]
             mv             a1, zero
+            ; gcrRegs +[a1]
             ld             a2, 0xD1FFAB1E(a0)
             ld             a2, 0xD1FFAB1E(a2)
             ld             a2, 0xD1FFAB1E(a2)

Looks like a bonus fix. Notice how this code I removed also silently stripped GC flags.

runtime/src/coreclr/jit/codegenriscv64.cpp

Lines 902 to 905 in f1cbe0f

    
           if (!compiler->opts.compReloc) 
        
           { 
        
               size = EA_SIZE(size); // Strip any Reloc flags from size if we aren't doing relocs. 
        
           }

JulieLeeMSFT · 2025-10-06T19:55:23Z

We will review .NET 11 PRs when we are done with .NET 10 last minute works and less busy. Please give us a few more weeks.
CC @jakobbotsch.

jakobbotsch · 2025-10-21T12:58:58Z

@EgorBo Do we need a fix for arm64 version of the code @tomeksowi points at above?

runtime/src/coreclr/jit/codegenarm64.cpp

Lines 2098 to 2101 in 25e088f

    
           if (!compiler->opts.compReloc) 
        
           { 
        
               size = EA_SIZE(size); // Strip any Reloc flags from size if we aren't doing relocs 
        
           }

For address 0 it is clearly not a problem -- would it be a problem for frozen objects?

jakobbotsch · 2025-10-21T13:06:21Z

If an address can be synthesized as PC-relative (2 instructions: auipc + ld/addi), do so.

Note that it's generally impossible to know where the code will be located, so you can only do this heuristically. How do you recover when you get it wrong?

For x64 we recover the situation by disabling rip-relative addressing globally the first time it happens, and then designing things so that it very rarely happens. Look for m_fAllowRel32.

EgorBo · 2025-10-21T17:10:35Z

@EgorBo Do we need a fix for arm64 version of the code @tomeksowi points at above?

Do you mean it may strip the GC related flags for frozen objects? I think we don't report them to GC anyway, do we?

tomeksowi · 2025-10-22T14:46:38Z

Note that it's generally impossible to know where the code will be located, so you can only do this heuristically. How do you recover when you get it wrong?

For x64 we recover the situation by disabling rip-relative addressing globally the first time it happens, and then designing things so that it very rarely happens. Look for m_fAllowRel32.

I don't recover, the address of a handle with function address was always within range, but you're right, IsIconHandle(GTF_ICON_FTN_ADDR) is just a heuristic. I remember looking at m_fAllowRel32 briefly but abandoned it because it seemed linked to jump stubs which RISC-V doesn't use (and aren't applicable here since we're doing loads for the handles).

I'll try to use it, maybe communicating failure with m_fJumpStubOverflow = TRUE to reuse existing codepaths, then eeGetRelocTypeHint on the handle value should tell me which way to go.

jakobbotsch · 2025-10-22T15:03:42Z

For x64 there is a contract between the JIT and VM about when and how relative addressing is used: for data addresses PC-relative addressing can only be used based on getRelocTypeHint. For code addresses PC-relative addressing can always be used, and the VM will create jump stubs if necessary.

If you are using PC-relative addressing for data addresses then I expect you need to build a similar system. If you are only using it for code addresses, then I expect you need to support some form of jump stubs.

jakobbotsch · 2025-10-22T15:14:18Z

@EgorBo Do we need a fix for arm64 version of the code @tomeksowi points at above?

Do you mean it may strip the GC related flags for frozen objects? I think we don't report them to GC anyway, do we?

Yes, that's what I meant. I was not sure if they GC refs to frozen objects need to be reported or not. If not then it seems ok.

EgorBo · 2025-10-22T15:41:25Z

@EgorBo Do we need a fix for arm64 version of the code @tomeksowi points at above?

Do you mean it may strip the GC related flags for frozen objects? I think we don't report them to GC anyway, do we?

Yes, that's what I meant. I was not sure if they GC refs to frozen objects need to be reported or not. If not then it seems ok.

I think in fact we do report them today, but don't have to

tomeksowi · 2025-11-18T08:29:29Z

OK, I cleared assumptions about code being always allocated within 32-bit range of the helper function. I also added jump stubs while I'm here.

Ready for review @jakobbotsch @dotnet/jit-contrib

jkotas · 2025-11-18T14:16:31Z

src/coreclr/vm/jitinterface.cpp

+
+            if (putTargetIntoAuipcCombo(target))
+                break; // success
+


Can this use the same structure as Amd64 and Arm64 cases?

jkotas · 2025-11-18T14:18:13Z

src/coreclr/vm/jitinterface.cpp

+                INT32 lo12 = (offset << (64 - 12)) >> (64 - 12);
+                INT32 hi20 = INT32(offset - lo12);
+
+                if (INT64(hi20) + INT64(lo12) != offset)


I think it would be better to move this into a FitsIn.... helper method that's next to PutRiscV64AuipcItype, and keep PutRiscV64AuipcItype signature as is so that callers do not need to be aware of the encoding details and limitations.

jkotas · 2025-11-18T14:19:28Z

src/coreclr/vm/jitinterface.cpp

+            enum
+            {
+                OpcodeJalr = 0x67,
+                OpcodeMask = 0x7F,


It would look better if there is a separate reloc type for IP vs. data so that we do not need to disassemble the instructions here.

src/coreclr/vm/jitinterface.cpp

am11

For linux-musl-riscv64

src/coreclr/vm/jitinterface.cpp

src/coreclr/inc/utilcode.h

src/coreclr/tools/superpmi/superpmi-shared/compileresult.cpp

Co-authored-by: Adeel Mujahid <3840695+am11@users.noreply.github.com>

src/coreclr/inc/corinfo.h

src/coreclr/inc/utilcode.h

am11 · 2025-11-20T08:50:14Z

src/coreclr/tools/Common/Compiler/ObjectWriter/ElfObjectWriter.cs

                    BinaryPrimitives.WriteInt64LittleEndian(relocationEntry.Slice(16), symbolicRelocation.Addend);
                    relocationStream.Write(relocationEntry);
+
+                    // TODO: This is wrong, LO12 needs to point to a label (previous instruction with HI20)


Suggested change

// TODO: This is wrong, LO12 needs to point to a label (previous instruction with HI20)

// TODO-RISCV64: This is wrong, LO12 needs to point to a label (previous instruction with HI20)

Up till this point in your PR, AOT smoke tests are passing on glibc and musl. If you have a repro, maybe would be nice to add a tests in one of the categories under src/tests/nativeaot/SmokeTests (or its own category) to make it clear what doesn't work.

CALL_PLT relocation is meant for auipc+jalr. Emitting it always (also for loads and addi) could have worked by mistake, these instructions have the same I-type layout as jalr. This won't be the case for stores as the S-type format is slightly different.

I came up with a relocation pattern that matches the ELF spec better:
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#pc-relative-symbol-addresses

In the future we may support hoisting the auipc for optimizations similar to #121739 but currently I'm pushing to get PC-relative ops widespread as being very frequent they bring significant savings over synthesizing absolute addresses.

But testing sounds a good idea, I'll try to add once I figure out how to build; it complains about objcopy in my env not recognizing the format (true) but ./src/tests/build.sh -cross -rebuild -nativeaot ... -p:ObjCopyName=/usr/bin/llvm-objcopy-18 doesn't have an effect

Ah, my workflow isn't propagating the exit code from qemu VM to host when test fails (I will see if it's possible at all since I thought it's handled by the if [ "$fail" -eq 1 ]; then exit 1; fi condition in workflow), but your branch is actually failing an AOT smoke test. I've checked it doesn't show up on main.

main: https://github.com/am11/CrossRepoCITesting/actions/runs/19540902736/job/55946632081 (git HEAD is at: 56ce9bd28dfd46b3b99d64825cea94b7bacbf4f3)

pr: https://github.com/am11/CrossRepoCITesting/actions/runs/19540949235/job/55946805017 (git HEAD is at: c2ab64490f307bf93e28bd734e649e958888b17d)

In run tests in qemu section, it shows:

-------------------------------- Running Test: Caught Unexpected exception:System.NullReferenceException: Object reference not set to an instance of an object. at CoreFXTestLibrary.Internal.Runner.RunTestMethod(TestInfo) + 0x414 at CoreFXTestLibrary.Internal.Runner.RunTest(TestInfo) + 0x48 ---- Test FAILED --------------- Unhandled exception. System.NullReferenceException: Object reference not set to an instance of an object. at CoreFXTestLibrary.Internal.Runner.RunTests(TestInfo[], String[]) + 0x80 at EntryPointMain.Main(String[] args) + 0x2a78 Aborted (core dumped)

But testing sounds a good idea, I'll try to add once I figure out how to build; it complains about objcopy in my env not recognizing the format (true) but ./src/tests/build.sh -cross -rebuild -nativeaot ... -p:ObjCopyName=/usr/bin/llvm-objcopy-18 doesn't have an effect

You can use llvm-objcopy from the toolchain. The container I am using is from dotnet prereqs repo, same one is used in CI here. They have all the build prerequisites installed (including llvm-objcopy; all tools in llvm toolchain are multi-target, so any host/target arch combo works).

src/coreclr/vm/jitinterface.cpp

…ion for LO12

github-actions bot added the area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI label Aug 29, 2025

dotnet-policy-service bot added the community-contribution Indicates that the PR has been added by a community member label Aug 29, 2025

This was referenced Aug 29, 2025

[android] Android.Device_Emulator.JIT.Test failing on emulators with CoreCLR #112633

Open

Sometimes the helix SDK uses GetWorkItemsAsync when workitems aren't done processing. dotnet/dnceng#6011

Open

tomeksowi added 3 commits August 31, 2025 23:41

Synthesize handles for function addresses with auipc+ld

77fdbb8

Use auipc+ld/addi for addresses also in non-compReloc

60ec4a9

Always record relocation

848ac99

clamp03 added the arch-riscv Related to the RISC-V architecture label Sep 1, 2025

clamp03 assigned tomeksowi Sep 1, 2025

tomeksowi added 3 commits September 1, 2025 15:30

clear gc info when address is built in register

65014e2

fix reloc type

b43e790

cleanup: emitAlllocInstr sets idGCref and idOpSize based on attr

bd0e79c

tomeksowi force-pushed the pc-rel-pointers branch from c2181d6 to bd0e79c Compare September 1, 2025 15:01

tomeksowi added 2 commits September 1, 2025 17:41

remove redundant assert

1f016da

remove unused debug fields

80bca29

tomeksowi marked this pull request as ready for review September 2, 2025 06:23

steveisok added this to the 11.0.0 milestone Oct 6, 2025

tomeksowi added 2 commits November 14, 2025 12:37

Centralize checking whether direct call is in range

ab556f8

jump stubs

e38cf3f

tomeksowi marked this pull request as ready for review November 18, 2025 08:03

jkotas reviewed Nov 18, 2025

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am11 mentioned this pull request Nov 18, 2025

[RISC-V] Enable constant CSE in RISCV64 #121739

Open

tomeksowi added 5 commits November 19, 2025 10:52

FitsIn

4c7f286

Add different relocation types to avoid telling jalr by disasm

315c807

Tell S-type by relocation type instead of disassembling the fixup site

5a5881e

comment

4b8d487

Refactor fix-up to use same code structure as arm64

2874ec4

tomeksowi requested a review from MichalStrehovsky as a code owner November 19, 2025 16:47

tomeksowi marked this pull request as draft November 19, 2025 16:47

tomeksowi added 2 commits November 19, 2025 17:52

Merge branch 'main' into pc-rel-pointers (resolve conflicts)

455bcb7

Use PCREL_I for ld

5b5ce0a

am11 reviewed Nov 19, 2025

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tomeksowi and others added 2 commits November 19, 2025 20:16

fix musl build

80a6998

Co-authored-by: Adeel Mujahid <3840695+am11@users.noreply.github.com>

lower bool

062652b

jkotas reviewed Nov 20, 2025

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kg reviewed Nov 20, 2025

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tomeksowi added 3 commits November 20, 2025 14:40

Add symbol for PC-relative HI20 relocation and record another relocat…

917fb8d

…ion for LO12

FitsInRiscV64

398e3b9

Explain where auipc combo bounds come from

c2ab644

	// TODO: This is wrong, LO12 needs to point to a label (previous instruction with HI20)
	// TODO-RISCV64: This is wrong, LO12 needs to point to a label (previous instruction with HI20)

[RISC-V] Synthesizing PC-relative pointer constants #119203

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[RISC-V] Synthesizing PC-relative pointer constants #119203

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Size improvements/regressions per collection

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jit-analyze output

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risc-vv commented Sep 1, 2025 •

edited

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