Always record relocation

tomeksowi · tomeksowi · commit c2181d6081bd · 2025-08-29T17:49:43.000+02:00
diff --git a/src/coreclr/inc/utilcode.h b/src/coreclr/inc/utilcode.h
@@ -3360,12 +3360,12 @@ void PutLoongArch64PC12(UINT32 * pCode, INT64 imm);
 void PutLoongArch64JIR(UINT32 * pCode, INT64 imm);
 
 //*****************************************************************************
-//  Extract the PC-Relative offset from auipc + I-type adder (addi/ld/jalr)
+//  Extract the PC-Relative offset from auipc + I-type adder (addi/load/jalr)
 //*****************************************************************************
 INT64 GetRiscV64AuipcItype(UINT32 * pCode);
 
 //*****************************************************************************
-//  Deposit the PC-Relative offset into auipc + I-type adder (addi/ld/jalr)
+//  Deposit the PC-Relative offset into auipc + I-type adder (addi/load/jalr)
 //*****************************************************************************
 void PutRiscV64AuipcItype(UINT32 * pCode, INT64 offset);
 
diff --git a/src/coreclr/jit/codegenriscv64.cpp b/src/coreclr/jit/codegenriscv64.cpp
@@ -902,10 +902,6 @@ void CodeGen::instGen_Set_Reg_To_Imm(emitAttr       size,
     assert(genIsValidIntReg(reg));
     if (EA_IS_RELOC(size))
     {
-        if (!compiler->opts.compReloc)
-        {
-            size = EA_SIZE(size); // Strip any Reloc flags from size if we aren't doing relocs.
-        }
         emit->emitIns_R_AI(INS_addi, size, reg, imm);
     }
     else
@@ -2426,6 +2422,11 @@ instruction CodeGen::genGetInsForOper(GenTree* treeNode)
                 break;
 
             default:
+
+                char message[256];
+                _snprintf_s(message, ArrLen(message), _TRUNCATE, "Unhandled oper in genGetInsForOper() - float: %s",
+                            GenTree::OpName(oper));
+                NYIRAW(message);
                 NO_WAY("Unhandled oper in genGetInsForOper() - float");
                 break;
         }
@@ -2743,8 +2744,7 @@ void CodeGen::genCodeForReturnTrap(GenTreeOp* tree)
         params.callType = EC_INDIR_R;
         params.ireg     = REG_DEFAULT_HELPER_CALL_TARGET;
 
-        emitAttr attr = compiler->opts.compReloc ? EA_PTR_DSP_RELOC : EA_PTRSIZE;
-        GetEmitter()->emitIns_R_AI(INS_ld, attr, params.ireg, (ssize_t)helperFunction.addr);
+        GetEmitter()->emitIns_R_AI(INS_ld, EA_PTR_DSP_RELOC, params.ireg, (ssize_t)helperFunction.addr);
         regSet.verifyRegUsed(params.ireg);
     }
 
@@ -3615,8 +3615,7 @@ void CodeGen::genEmitHelperCall(unsigned helper, int argSize, emitAttr retSize,
         // assert that all registers in callTargetMask are in the callKillSet
         noway_assert((callTargetMask & killSet) == callTargetMask);
 
-        emitAttr attr = compiler->opts.compReloc ? EA_PTR_DSP_RELOC : EA_PTRSIZE;
-        GetEmitter()->emitIns_R_AI(INS_ld, attr, callTargetReg, (ssize_t)pAddr);
+        GetEmitter()->emitIns_R_AI(INS_ld, EA_PTR_DSP_RELOC, callTargetReg, (ssize_t)pAddr);
         regSet.verifyRegUsed(callTargetReg);
 
         params.callType = EC_INDIR_R;
@@ -4420,8 +4419,7 @@ void CodeGen::genSetGSSecurityCookie(regNumber initReg, bool* pInitRegZeroed)
     }
     else
     {
-        emitAttr attr = compiler->opts.compReloc ? EA_PTR_DSP_RELOC : EA_PTRSIZE;
-        emit->emitIns_R_AI(INS_ld, attr, initReg, (ssize_t)compiler->gsGlobalSecurityCookieAddr);
+        emit->emitIns_R_AI(INS_ld, EA_PTR_DSP_RELOC, initReg, (ssize_t)compiler->gsGlobalSecurityCookieAddr);
 
         regSet.verifyRegUsed(initReg);
         emit->emitIns_S_R(INS_sd, EA_PTRSIZE, initReg, compiler->lvaGSSecurityCookie, 0);
@@ -4456,8 +4454,7 @@ void CodeGen::genEmitGSCookieCheck(bool pushReg)
     else
     {
         // AOT case - GS cookie constant needs to be accessed through an indirection.
-        emitAttr attr = compiler->opts.compReloc ? EA_PTR_DSP_RELOC : EA_PTRSIZE;
-        GetEmitter()->emitIns_R_AI(INS_ld, attr, regGSConst, (ssize_t)compiler->gsGlobalSecurityCookieAddr);
+        GetEmitter()->emitIns_R_AI(INS_ld, EA_PTR_DSP_RELOC, regGSConst, (ssize_t)compiler->gsGlobalSecurityCookieAddr);
         regSet.verifyRegUsed(regGSConst);
     }
     // Load this method's GS value from the stack frame
@@ -6481,8 +6478,7 @@ void CodeGen::genJumpToThrowHlpBlk_la(
             // TODO-RISCV64-RVC: Remove hardcoded branch offset here
             ssize_t imm = (3 + 1) << 2;
             emit->emitIns_R_R_I(ins, EA_PTRSIZE, reg1, reg2, imm);
-            emitAttr attr = compiler->opts.compReloc ? EA_PTR_DSP_RELOC : EA_PTRSIZE;
-            emit->emitIns_R_AI(INS_ld, attr, params.ireg, (ssize_t)pAddr);
+            emit->emitIns_R_AI(INS_ld, EA_PTR_DSP_RELOC, params.ireg, (ssize_t)pAddr);
             regSet.verifyRegUsed(params.ireg);
         }
 
diff --git a/src/coreclr/jit/emitriscv64.cpp b/src/coreclr/jit/emitriscv64.cpp
@@ -94,7 +94,7 @@ size_t emitter::emitSizeOfInsDsc(instrDesc* id) const
 
         case INS_OPTS_RC:
         case INS_OPTS_RL:
-        case INS_OPTS_PCREL:
+        case INS_OPTS_RELOC:
         case INS_OPTS_NONE:
             return sizeof(instrDesc);
         case INS_OPTS_I:
@@ -1242,12 +1242,14 @@ void emitter::emitIns_R_AR(instruction ins, emitAttr attr, regNumber ireg, regNu
     NYI_RISCV64("emitIns_R_AR-----unimplemented/unused on RISCV64 yet----");
 }
 
-// This computes address from the immediate which is PC-relative.
+// This computes address from the immediate which is relocatable.
 void emitter::emitIns_R_AI(instruction  ins,
                            emitAttr     attr,
                            regNumber    reg,
                            ssize_t addr DEBUGARG(size_t targetHandle) DEBUGARG(GenTreeFlags gtFlags))
 {
+    assert(EA_IS_RELOC(attr));
+    assert(ins == INS_addi || emitInsIsLoad(ins));
     assert(isGeneralRegister(reg));
     // 2-ins:
     //   auipc  reg, off-hi-20bits
@@ -1259,7 +1261,7 @@ void emitter::emitIns_R_AI(instruction  ins,
     assert(reg != REG_R0); // for special. reg Must not be R0.
     id->idReg1(reg);       // destination register that will get the constant value.
 
-    id->idInsOpt(INS_OPTS_PCREL);
+    id->idInsOpt(INS_OPTS_RELOC);
 
     id->idOpSize(EA_SIZE(attr));
     if (EA_IS_GCREF(attr))
@@ -3198,32 +3200,18 @@ static ssize_t UpperWordOfDoubleWordDoubleSignExtend(ssize_t doubleWord)
     return static_cast<unsigned>(LowerNBitsOfWord<21>(imm21));
 }
 
-BYTE* emitter::emitOutputInstr_OptsPcRel(BYTE* dst, const instrDesc* id, instruction* ins)
+BYTE* emitter::emitOutputInstr_OptsReloc(BYTE* dst, const instrDesc* id, instruction* ins)
 {
     BYTE* const     dstBase = dst;
     const regNumber reg1    = id->idReg1();
     assert(isGeneralRegister(reg1));
 
-    unsigned hi20 = 0;
-    unsigned lo12 = 0;
-    if (!id->idIsReloc())
-    {
-        UNATIVE_OFFSET srcOffs  = emitCurCodeOffs(dst);
-        const BYTE*    srcAddr  = emitOffsetToPtr(srcOffs);
-        ssize_t        distance = (ssize_t)(id->idAddr()->iiaAddr - srcAddr);
-        assert(isValidSimm32(distance));
-        hi20 = UpperNBitsOfWordSignExtend<20>(distance);
-        lo12 = LowerNBitsOfWord<12>(distance);
-    }
-
     *ins = id->idIns();
     assert(*ins == INS_addi || emitInsIsLoad(*ins));
-    dst += emitOutput_UTypeInstr(dst, INS_auipc, reg1, hi20);
-    dst += emitOutput_ITypeInstr(dst, *ins, reg1, reg1, lo12);
-
-    if (id->idIsReloc())
-        emitRecordRelocation(dstBase, id->idAddr()->iiaAddr, IMAGE_REL_RISCV64_PC);
+    dst += emitOutput_UTypeInstr(dst, INS_auipc, reg1, 0);
+    dst += emitOutput_ITypeInstr(dst, *ins, reg1, reg1, 0);
 
+    emitRecordRelocation(dstBase, id->idAddr()->iiaAddr, IMAGE_REL_RISCV64_PC);
     return dst;
 }
 
@@ -3431,8 +3419,8 @@ size_t emitter::emitOutputInstr(insGroup* ig, instrDesc* id, BYTE** dp)
 
     switch (insOp)
     {
-        case INS_OPTS_PCREL:
-            dst = emitOutputInstr_OptsPcRel(dst, id, &ins);
+        case INS_OPTS_RELOC:
+            dst = emitOutputInstr_OptsReloc(dst, id, &ins);
             sz  = sizeof(instrDesc);
             break;
         case INS_OPTS_RC:
@@ -5153,7 +5141,7 @@ void emitter::emitInsLoadStoreOp(instruction ins, emitAttr attr, regNumber dataR
 
                 if (addr->IsIconHandle(GTF_ICON_FTN_ADDR))
                 {
-                    emitIns_R_AI(ins, attr, dataReg, (size_t)cns, cns, addr->GetIconHandleFlag());
+                    emitIns_R_AI(ins, EA_PTR_DSP_RELOC, dataReg, (size_t)cns, cns, addr->GetIconHandleFlag());
                 }
                 else
                 {
diff --git a/src/coreclr/jit/emitriscv64.h b/src/coreclr/jit/emitriscv64.h
@@ -135,7 +135,7 @@ unsigned emitOutput_BTypeInstr_InvertComparation(
     BYTE* dst, instruction ins, regNumber rs1, regNumber rs2, unsigned imm13) const;
 unsigned emitOutput_JTypeInstr(BYTE* dst, instruction ins, regNumber rd, unsigned imm21) const;
 
-BYTE* emitOutputInstr_OptsPcRel(BYTE* dst, const instrDesc* id, instruction* ins);
+BYTE* emitOutputInstr_OptsReloc(BYTE* dst, const instrDesc* id, instruction* ins);
 BYTE* emitOutputInstr_OptsRc(BYTE* dst, const instrDesc* id, instruction* ins);
 BYTE* emitOutputInstr_OptsRl(BYTE* dst, instrDesc* id, instruction* ins);
 BYTE* emitOutputInstr_OptsJalr(BYTE* dst, instrDescJmp* jmp, const insGroup* ig, instruction* ins);
diff --git a/src/coreclr/jit/instr.h b/src/coreclr/jit/instr.h
@@ -558,7 +558,7 @@ enum insOpts : unsigned
     INS_OPTS_J_cond, // see ::emitIns_J_cond_la().
     INS_OPTS_I,      // see ::emitLoadImmediate().
     INS_OPTS_C,      // see ::emitIns_Call().
-    INS_OPTS_PCREL,  // see ::emitIns_R_AI().
+    INS_OPTS_RELOC,  // see ::emitIns_R_AI().
 };
 
 enum insBarrier : unsigned
diff --git a/src/coreclr/tools/superpmi/superpmi-shared/spmiutil.cpp b/src/coreclr/tools/superpmi/superpmi-shared/spmiutil.cpp
@@ -478,30 +478,33 @@ void PutArm32MovtConstant(UINT32* p, unsigned con)
 }
 
 //*****************************************************************************
-//  Extract the PC-Relative offset from auipc + I-type adder (addi/ld/jalr)
+//  Extract the PC-Relative offset from auipc + I-type adder (addi/load/jalr)
 //*****************************************************************************
 INT64 GetRiscV64AuipcItype(UINT32 * pCode)
 {
     enum
     {
-        OpcodeAuipc = 0x00000017,
-        OpcodeAddi = 0x00000013,
-        OpcodeLd = 0x00003003,
-        OpcodeJalr = 0x00000067,
-        OpcodeUTypeMask = 0x0000007F,
-        OpcodeITypeMask = 0x0000307F,
+        OpcodeAuipc = 0x17,
+        OpcodeAddi = 0x13,
+        OpcodeLoad = 0x03,
+        OpcodeJalr = 0x67,
+        OpcodeMask = 0x7F,
+
+        Funct3AddiJalr = 0x0000,
+        Funct3Mask = 0x7000,
     };
 
     UINT32 auipc = pCode[0];
-    _ASSERTE((auipc & OpcodeUTypeMask) == OpcodeAuipc);
+    _ASSERTE((auipc & OpcodeMask) == OpcodeAuipc);
     int auipcRegDest = (auipc >> 7) & 0x1F;
     _ASSERTE(auipcRegDest != 0);
 
     INT64 hi20 = (INT32(auipc) >> 12) << 12;
 
     UINT32 iType = pCode[1];
-    UINT32 opcode = iType & OpcodeITypeMask;
-    _ASSERTE(opcode == OpcodeAddi || opcode == OpcodeLd || opcode == OpcodeJalr);
+    UINT32 opcode = iType & OpcodeMask;
+    UINT32 funct3 = iType & Funct3Mask;
+    _ASSERTE(opcode == OpcodeLoad || ((opcode == OpcodeAddi || opcode == OpcodeJalr) && funct3 == Funct3AddiJalr));
     int iTypeRegSrc = (iType >> 15) & 0x1F;
     _ASSERTE(auipcRegDest == iTypeRegSrc);
 
diff --git a/src/coreclr/utilcode/util.cpp b/src/coreclr/utilcode/util.cpp
@@ -2334,30 +2334,33 @@ void PutLoongArch64JIR(UINT32 * pCode, INT64 imm38)
 
 
 //*****************************************************************************
-//  Extract the PC-Relative offset from auipc + I-type adder (addi/ld/jalr)
+//  Extract the PC-Relative offset from auipc + I-type adder (addi/load/jalr)
 //*****************************************************************************
 INT64 GetRiscV64AuipcItype(UINT32 * pCode)
 {
     enum
     {
-        OpcodeAuipc = 0x00000017,
-        OpcodeAddi = 0x00000013,
-        OpcodeLd = 0x00003003,
-        OpcodeJalr = 0x00000067,
-        OpcodeUTypeMask = 0x0000007F,
-        OpcodeITypeMask = 0x0000307F,
+        OpcodeAuipc = 0x17,
+        OpcodeAddi = 0x13,
+        OpcodeLoad = 0x03,
+        OpcodeJalr = 0x67,
+        OpcodeMask = 0x7F,
+
+        Funct3AddiJalr = 0x0000,
+        Funct3Mask = 0x7000,
     };
 
     UINT32 auipc = pCode[0];
-    _ASSERTE((auipc & OpcodeUTypeMask) == OpcodeAuipc);
+    _ASSERTE((auipc & OpcodeMask) == OpcodeAuipc);
     int auipcRegDest = (auipc >> 7) & 0x1F;
     _ASSERTE(auipcRegDest != 0);
 
     INT64 hi20 = (INT32(auipc) >> 12) << 12;
 
     UINT32 iType = pCode[1];
-    UINT32 opcode = iType & OpcodeITypeMask;
-    _ASSERTE(opcode == OpcodeAddi || opcode == OpcodeLd || opcode == OpcodeJalr);
+    UINT32 opcode = iType & OpcodeMask;
+    UINT32 funct3 = iType & Funct3Mask;
+    _ASSERTE(opcode == OpcodeLoad || ((opcode == OpcodeAddi || opcode == OpcodeJalr) && funct3 == Funct3AddiJalr));
     int iTypeRegSrc = (iType >> 15) & 0x1F;
     _ASSERTE(auipcRegDest == iTypeRegSrc);
 
