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Sama7g5 USB UDC (UDPHS) driver #99620
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Sama7g5 USB UDC (UDPHS) driver #99620
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| USB packets system data bursts will be locked for | ||
| maximum optimization of the bus bandwidth usage. |
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I have no idea what this really means. From code it seems that you set some bit. Is it essentially affecting DMA operation/memory access arbitrage?
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Hi, this is a chip related feature, for more details please refer to the datasheet, see bit BURST_LCK in register UDPHS_DMACONTROL.
This will allow the UDPHS DMA channel has max burst length when accessing the bus.
And I made a switch for this feature in the Kconfig, customer can enable it for higher USB bandwidth under heavy system load.
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Add a report from sample/subsys/usb/testusb HS. FS is it should work like that too.
A full report usually tests from 0 up to 29.
| }; | ||
| }; | ||
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| udphsa: usbd@200000 { |
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Convention is order by address.
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The devices in sama7g5.dtsi have been listed in alphabetical order, so I put the udphs device at the end of it.
Do you still need me order the udphs devices by space address?
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| compatible: "microchip,sam-udphs" | ||
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| include: [usb-ep.yaml, pinctrl-device.yaml] |
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zephyr/dts/bindings/ethernet/atmel,gmac-common.yaml
Lines 5 to 7 in db0c34d
| include: | |
| - name: ethernet-controller.yaml | |
| - name: pinctrl-device.yaml |
-include: [usb-ep.yaml, pinctrl-device.yaml]
+include:
+ - name: usb-ep.yaml
+ - name: pinctrl-device.yamlThere was a problem hiding this comment.
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Updated.
| (MMU_REGION_FLAT_ENTRY("pwm", PWM_BASE_ADDRESS, 0x500, | ||
| MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),)) | ||
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| MMU_REGION_FLAT_ENTRY("rstc", RSTC_BASE_ADDRESS, 0x10, |
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by convention we are enabling this before devicetree binding. Move this commit to 2nd position.
Note: Adjust the commit message body to be close to the 72 character per line.
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Commits order has been adjusted.
Commit message body has been adjusted.
drivers/usb/udc/Kconfig.mchp_sam
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| config UDC_MCHP_SAM_BURST_LOCK | ||
| bool "Lock bus access for maximum bandwidth" | ||
| default n |
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I think the default n can be dropped because it is the default. See redundant-defaults. Drop all redundant defaults.
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All redundant defaults have been removed.
| #define SZ_1024 10 /* 1 << 10 */ | ||
| }; | ||
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| static const struct udphs_ep_desc sam_ep_desc[UDPHS_EPT_NUMBER] = { |
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By this table the driver will only expose HS, no FS. Is that right ?
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No, this table exposed all endpoints for HS and FS.
These endpoints can be used in HS mode and FS mode.
Add api function to check the setup stage, which means the control transfer's stages are completed and back to the default stage. Signed-off-by: CHEN Xing <xing.chen@microchip.com>
Update mmu region for udphsa and udphsb, add usb phy clock configuration Signed-off-by: CHEN Xing <xing.chen@microchip.com>
Add udphsa udphsb udc devices to sama7g5 Signed-off-by: CHEN Xing <xing.chen@microchip.com>
Add driver for sama7g5 UDPHS Signed-off-by: CHEN Xing <xing.chen@microchip.com>
Add udphs udc devices and enable udphsa Signed-off-by: CHEN Xing <xing.chen@microchip.com>
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Hi Gerson, Many thanks. |
If I'm not mistake, 10 is about data out in control EP. The below could give you some hints. |



Add driver support for Sama7g5 USB UDC (UDPHS).
Many thanks.
Xing.