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intel_adsp: ace: secondary core context save and restore #55182

Merged
merged 5 commits into from
Apr 28, 2023
Merged

intel_adsp: ace: secondary core context save and restore #55182

merged 5 commits into from
Apr 28, 2023

Commits on Apr 26, 2023

  1. intel_adsp: ace: add stack for other cores 

    This patch replace temporary stack of the restore vector with interrupt
stack to reduce memory usage. Additionally we can assign seprate stack
for each core. This will allow to reuse this vector for secondary cores.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
    @tmleman
    tmleman committed Apr 26, 2023
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  2. intel_adsp: ace: cpu context save refactor 

    This patch is preparing cpu context save and restore code so it can be
later used by the multiple cores.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
    @tmleman
    tmleman committed Apr 26, 2023
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  3. intel_adsp: ace: secondary core context restore 

    Reusing primary core context save/restore flow for purpose of secondary
core D0 -> D3 -> D0 transitions. If core is re-enabled we use
dsp_restore_vector as the FW entry point.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
    @tmleman
    tmleman committed Apr 26, 2023
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  4. intel_adsp: power: ace: interrupts on and off 

    Masking out all interrupt during power state transition and restoring
them after is now common thing for all power states. No need to
duplicate code.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
    @tmleman
    tmleman committed Apr 26, 2023
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  5. intel_adsp: power: ace: cache invalidation 

    This patch moves cache flush/invalidation to section executed only when
IMR context saving is enabled. If this option is disabled no FW context
is stored so any lost data doesn't matter.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
    @tmleman
    tmleman committed Apr 26, 2023
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