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intel_adsp: ace: secondary core context save and restore #55182
intel_adsp: ace: secondary core context save and restore #55182
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Can we clean this up? It seems like you needed a way to tell whether or not a core was being started up after initial boot, and decided to abuse the kernel thread state for the idle thread? That's... no, that's just not right. Those are different subsystems. If the arch/soc code needs to track state for its own purposes, it needs to do it on its own and not repurpose other code from other areas.
FWIW: looking at that soc_cpus_active[] array, I'm guessing that's the right kind of abstraction to be using (though it seems to have been broken by this PR?).
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@andyross please take a look at the updated versions now. |
@andyross friendly reminder |
Adding DNM label because of thesofproject/sof#7433. After this PR is merged zephyr update on SOF side will require additional changes. This would make later bisect more difficult in case of any new problems. But you can still review and approve. |
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I'm still a little bit skeptical about the need of all flush/invalidate cache but you know better than me about it here
This patch replace temporary stack of the restore vector with interrupt stack to reduce memory usage. Additionally we can assign seprate stack for each core. This will allow to reuse this vector for secondary cores. Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch is preparing cpu context save and restore code so it can be later used by the multiple cores. Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Reusing primary core context save/restore flow for purpose of secondary core D0 -> D3 -> D0 transitions. If core is re-enabled we use dsp_restore_vector as the FW entry point. Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Masking out all interrupt during power state transition and restoring them after is now common thing for all power states. No need to duplicate code. Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This patch moves cache flush/invalidation to section executed only when IMR context saving is enabled. If this option is disabled no FW context is stored so any lost data doesn't matter. Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
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Rebase after merge of #50136 |
Ignore, added DNM by accident to wrong PR. |
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Saw this come by again. Looks great to me, my concerns earlier were all addressed.
Reusing primary core context save/restore flow for purpose of secondary core D0 -> D3 -> D0 transitions.
FW on secondary core when preparing for D3 will save its context. When core is re-enabled we use dsp_restore_vector as the FW entry point.