drivers: gpio: sifive: Fix GPIO extern interrupts

[nategraff-sifive]

GPIO external interrupt lines need to be offset by RISCV_MAX_GENERIC_IRQ. I missed this when I converted the SiFive GPIO driver to support DeviceTree and it broke GPIO external interrupts.

[codecov-io]

Codecov Report

Merging #10613 into master will not change coverage.
The diff coverage is n/a.

@@           Coverage Diff           @@
##           master   #10613   +/-   ##
=======================================
  Coverage   53.19%   53.19%           
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  Files         211      211           
  Lines       25828    25828           
  Branches     5686     5686           
=======================================
  Hits        13738    13738           
  Misses       9781     9781           
  Partials     2309     2309

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[nmeum]

Shouldn't a similar change be necessary for other external interrupt sources as well? For example drivers/serial/uart_sifive.c. Because I noticed that, for IRQ 4 (UART1) riscv_plic_irq_enable is not called (even though UART1 is an external interrupt source) because 4 <= RISCV_MAX_GENERIC_IRQ.

zephyr/soc/riscv32/riscv-privilege/common/soc_common_irq.c

Lines 14 to 32 in 4344e27

	void z_arch_irq_enable(unsigned int irq)
	{
	u32_t mie;
	#if defined(CONFIG_RISCV_HAS_PLIC)
	if (irq > RISCV_MAX_GENERIC_IRQ) {
	riscv_plic_irq_enable(irq);
	return;
	}
	#endif
	/*
	* CSR mie register is updated using atomic instruction csrrs
	* (atomic read and set bits in CSR register)
	*/
	__asm__ volatile ("csrrs %0, mie, %1\n"
	: "=r" (mie)
	: "r" (1 << irq));
	}