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Add timescale option to SlangConfig (#20)
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sherbst-openai authored Nov 19, 2024
1 parent 951867c commit 1256b7c
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Showing 4 changed files with 55 additions and 2 deletions.
2 changes: 1 addition & 1 deletion Cargo.lock

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2 changes: 1 addition & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
[package]
name = "slang-rs"
version = "0.11.0"
version = "0.12.0"
edition = "2021"
license = "Apache-2.0"
description = "Rust bindings for the Slang Verilog parser"
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7 changes: 7 additions & 0 deletions src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,7 @@ pub struct SlangConfig<'a> {
pub libdirs: &'a [&'a str],
pub libexts: &'a [&'a str],
pub ignore_unknown_modules: bool,
pub timescale: Option<&'a str>,
}

impl<'a> Default for SlangConfig<'a> {
Expand All @@ -32,6 +33,7 @@ impl<'a> Default for SlangConfig<'a> {
libdirs: &[],
libexts: &[],
ignore_unknown_modules: true,
timescale: None,
}
}
}
Expand Down Expand Up @@ -112,6 +114,11 @@ pub fn run_slang(cfg: &SlangConfig) -> Result<Value, Box<dyn std::error::Error>>
args.push(libext);
}

if let Some(timescale) = cfg.timescale {
args.push("--timescale");
args.push(timescale);
}

for source in cfg.sources.iter() {
args.push(source);
}
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46 changes: 46 additions & 0 deletions tests/test.rs
Original file line number Diff line number Diff line change
Expand Up @@ -671,4 +671,50 @@ endmodule

assert_eq!(modules, vec!["A", "B", "C", "D"]);
}

#[test]
fn test_timescale_option() {
let verilog_a = str2tmpfile(
"
module A(
input clk
);
B b();
endmodule
",
)
.unwrap();

let verilog_b = str2tmpfile(
"
`timescale 1ns/1ps
module B;
endmodule
",
)
.unwrap();

let cfg = SlangConfig {
sources: &[
verilog_b.path().to_str().unwrap(),
verilog_a.path().to_str().unwrap(),
],
tops: &["A"],
timescale: Some("1ns/1ps"),
..Default::default()
};

assert_eq!(
extract_ports(&cfg, false)["A"],
vec![Port {
dir: PortDir::Input,
name: "clk".to_string(),
ty: Type::Logic {
signed: false,
packed_dimensions: vec![],
unpacked_dimensions: vec![]
},
}]
);
}
}

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