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Merge pull request eclipse-omr#5193 from hzongaro/unsupported-value-t…
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…ype-is-recoverable

Make UnsupportedValueTypeOperation a recoverable exception
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@andrewcraik @wbh123456
andrewcraik authored and wbh123456 committed Jun 9, 2020
2 parents c65b0bc + 054dc9b commit baea80a
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Showing 4 changed files with 55 additions and 138 deletions.
22 changes: 11 additions & 11 deletions compiler/compile/CompilationException.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -65,17 +65,6 @@ struct ILGenFailure : public virtual CompilationException
virtual const char* what() const throw() { return "IL Gen Failure"; }
};

/**
* Unsupported value type operation exception type.
*
* Thrown if an unsupported value type operation is encountered that requires
* compilation to be aborted.
*/
struct UnsupportedValueTypeOperation : public virtual CompilationException
{
virtual const char* what() const throw() { return "Unsupported value type operation"; }
};

/**
* Recoverable IL Generation Failure exception type.
*
Expand All @@ -100,6 +89,17 @@ struct NoRecompilationRecoverableILGenException: public RecoverableILGenExceptio
virtual const char* what() const throw() { return "Recoverable IL Gen Exception with no recompilation if failing method is outermost"; }
};

/**
* Unsupported value type operation exception type.
*
* Thrown if an unsupported value type operation is encountered that requires
* compilation to be aborted.
*/
struct UnsupportedValueTypeOperation : public virtual RecoverableILGenException
{
virtual const char* what() const throw() { return "Unsupported value type operation"; }
};

/**
* Excessive Complexity exception type.
*
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7 changes: 6 additions & 1 deletion compiler/p/codegen/OMRCodeGenerator.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -401,8 +401,13 @@ OMR::Power::CodeGenerator::generateSwitchToInterpreterPrePrologue(

// gr0 must contain the saved LR; see Recompilation.s
cursor = new (self()->trHeapMemory()) TR::PPCTrg1Instruction(TR::InstOpCode::mflr, node, gr0, cursor, self());
<<<<<<< HEAD
cursor = self()->getLinkage()->flushArguments(cursor);
cursor = generateDepImmSymInstruction(self(), TR::InstOpCode::bl, node, (uintptr_t)revertToInterpreterSymRef->getMethodAddress(), new (self()->trHeapMemory()) TR::RegisterDependencyConditions(0,0, self()->trMemory()), revertToInterpreterSymRef, NULL, cursor);
=======
cursor = self()->getLinkage()->flushOrloadUpArguments(cursor, true);
cursor = generateDepImmSymInstruction(self(), TR::InstOpCode::bl, node, (uintptrj_t)revertToInterpreterSymRef->getMethodAddress(), new (self()->trHeapMemory()) TR::RegisterDependencyConditions(0,0, self()->trMemory()), revertToInterpreterSymRef, NULL, cursor);
>>>>>>> 1e25c79a3... Unify load and flush argument functions

if (self()->comp()->target().is64Bit())
{
Expand Down Expand Up @@ -1686,7 +1691,7 @@ void OMR::Power::CodeGenerator::generateBinaryEncodingPrologue(
data->jitTojitStart = data->cursorInstruction;
data->cursorInstruction = NULL;

self()->getLinkage()->loadUpArguments(data->cursorInstruction);
self()->getLinkage()->flushOrloadUpArguments(data->cursorInstruction, false);

data->cursorInstruction = self()->getFirstInstruction();

Expand Down
160 changes: 36 additions & 124 deletions compiler/p/codegen/OMRLinkage.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -495,12 +495,7 @@ TR::Instruction *OMR::Power::Linkage::saveArguments(TR::Instruction *cursor, boo
return(cursor);
}

TR::Instruction *OMR::Power::Linkage::loadUpArguments(TR::Instruction *cursor)
{
if (!self()->cg()->buildInterpreterEntryPoint())
// would be better to use a different linkage for this purpose
return cursor;

TR::Instruction *OMR::Power::Linkage::flushOrloadUpArguments(TR::Instruction *cursor, bool flush){
TR::Machine *machine = self()->machine();
TR::RealRegister *stackPtr = self()->cg()->getStackPointerRegister();
TR::ResolvedMethodSymbol *bodySymbol = self()->comp()->getJittedMethodSymbol();
Expand All @@ -517,153 +512,68 @@ TR::Instruction *OMR::Power::Linkage::loadUpArguments(TR::Instruction *cursor)
TR::RealRegister *argRegister;
int32_t offset = paramCursor->getParameterOffset();

bool hasToLoadFromStack = paramCursor->isReferencedParameter() || paramCursor->isParmHasToBeOnStack();
// If parm is referenced or required to be on stack (i.e. FSD), we have to flush or load.
bool hasToStoreOrLoadStack = paramCursor->isReferencedParameter() || paramCursor->isParmHasToBeOnStack();

switch (paramCursor->getDataType())
{
case TR::Int8:
case TR::Int16:
case TR::Int32:
if (hasToLoadFromStack &&
if (hasToStoreOrLoadStack &&
numIntArgs<properties.getNumIntArgRegs())
{
argRegister = machine->getRealRegister(properties.getIntegerArgumentRegister(numIntArgs));
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lwz, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()), cursor);
}
numIntArgs++;
break;
case TR::Address:
if (numIntArgs<properties.getNumIntArgRegs())
{
argRegister = machine->getRealRegister(properties.getIntegerArgumentRegister(numIntArgs));
cursor = generateTrg1MemInstruction(self()->cg(),TR::InstOpCode::Op_load, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, TR::Compiler->om.sizeofReferenceAddress(), self()->cg()), cursor);
}
numIntArgs++;
break;
case TR::Int64:
if (hasToLoadFromStack &&
numIntArgs<properties.getNumIntArgRegs())
{
argRegister = machine->getRealRegister(properties.getIntegerArgumentRegister(numIntArgs));
if (self()->comp()->target().is64Bit())
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::ld, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 8, self()->cg()), cursor);
else
{
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lwz, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()), cursor);
if (numIntArgs < properties.getNumIntArgRegs()-1)
{
argRegister = machine->getRealRegister(properties.getIntegerArgumentRegister(numIntArgs+1));
cursor = flush ? generateMemSrc1Instruction(self()->cg(), TR::InstOpCode::stw, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()),
argRegister, cursor):
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lwz, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset+4, 4, self()->cg()), cursor);
}
}
}
if (self()->comp()->target().is64Bit())
numIntArgs++;
else
numIntArgs+=2;
break;

case TR::Float:
case TR::Double:
if (hasToLoadFromStack &&
numFloatArgs<properties.getNumFloatArgRegs())
{
argRegister = machine->getRealRegister(properties.getFloatArgumentRegister(numFloatArgs));

TR::InstOpCode::Mnemonic op;
int32_t length;

if (paramCursor->getDataType() == TR::Float)
{
op = TR::InstOpCode::lfs; length = 4;
}
else
{
op = TR::InstOpCode::lfd; length = 8;
}

cursor = generateTrg1MemInstruction(self()->cg(), op, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, length, self()->cg()), cursor);
}
numFloatArgs++;
break;
}
paramCursor = paramIterator.getNext();
}
return(cursor);
}

TR::Instruction *OMR::Power::Linkage::flushArguments(TR::Instruction *cursor)
{
TR::Machine *machine = self()->machine();
TR::RealRegister *stackPtr = self()->cg()->getStackPointerRegister();
TR::ResolvedMethodSymbol *bodySymbol = self()->comp()->getJittedMethodSymbol();
ListIterator<TR::ParameterSymbol> paramIterator(&(bodySymbol->getParameterList()));
TR::ParameterSymbol *paramCursor = paramIterator.getFirst();
TR::Node *firstNode = self()->comp()->getStartTree()->getNode();
int32_t numIntArgs = 0, numFloatArgs = 0;
const TR::PPCLinkageProperties& properties = self()->getProperties();

while ( (paramCursor!=NULL) &&
( (numIntArgs < properties.getNumIntArgRegs()) ||
(numFloatArgs < properties.getNumFloatArgRegs()) ) )
{
TR::RealRegister *argRegister;
int32_t offset = paramCursor->getParameterOffset();

// If parm is referenced or required to be on stack (i.e. FSD), we have to flush.
bool hasToStoreToStack = paramCursor->isReferencedParameter() || paramCursor->isParmHasToBeOnStack();
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()), cursor);

switch (paramCursor->getDataType())
{
case TR::Int8:
case TR::Int16:
case TR::Int32:
if (hasToStoreToStack &&
numIntArgs<properties.getNumIntArgRegs())
{
argRegister = machine->getRealRegister(properties.getIntegerArgumentRegister(numIntArgs));
cursor = generateMemSrc1Instruction(self()->cg(), TR::InstOpCode::stw, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()),
argRegister, cursor);
}
numIntArgs++;
break;
case TR::Address:
if (numIntArgs<properties.getNumIntArgRegs())
{
argRegister = machine->getRealRegister(properties.getIntegerArgumentRegister(numIntArgs));
cursor = generateMemSrc1Instruction(self()->cg(),TR::InstOpCode::Op_st, firstNode,
cursor = flush? generateMemSrc1Instruction(self()->cg(),TR::InstOpCode::Op_st, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, TR::Compiler->om.sizeofReferenceAddress(), self()->cg()),
argRegister, cursor);
argRegister, cursor):
cursor = generateTrg1MemInstruction(self()->cg(),TR::InstOpCode::Op_load, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, TR::Compiler->om.sizeofReferenceAddress(), self()->cg()), cursor);
}
numIntArgs++;
break;
case TR::Int64:
if (hasToStoreToStack &&
if (hasToStoreOrLoadStack &&
numIntArgs<properties.getNumIntArgRegs())
{
argRegister = machine->getRealRegister(properties.getIntegerArgumentRegister(numIntArgs));
if (self()->comp()->target().is64Bit())
cursor = generateMemSrc1Instruction(self()->cg(),TR::InstOpCode::Op_st, firstNode,
{
cursor = flush ? generateMemSrc1Instruction(self()->cg(),TR::InstOpCode::Op_st, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 8, self()->cg()),
argRegister, cursor);
argRegister, cursor):
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::ld, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 8, self()->cg()), cursor);
}
else
{
cursor = generateMemSrc1Instruction(self()->cg(), TR::InstOpCode::stw, firstNode,
cursor = flush? generateMemSrc1Instruction(self()->cg(), TR::InstOpCode::stw, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()),
argRegister, cursor);
argRegister, cursor) :
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lwz, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, 4, self()->cg()), cursor);

if (numIntArgs < properties.getNumIntArgRegs()-1)
{
argRegister = machine->getRealRegister(properties.getIntegerArgumentRegister(numIntArgs+1));
cursor = generateMemSrc1Instruction(self()->cg(), TR::InstOpCode::stw, firstNode,
cursor = flush ? generateMemSrc1Instruction(self()->cg(), TR::InstOpCode::stw, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset+4, 4, self()->cg()),
argRegister, cursor);
argRegister, cursor):
cursor = generateTrg1MemInstruction(self()->cg(), TR::InstOpCode::lwz, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset+4, 4, self()->cg()), cursor);
}
}
}
Expand All @@ -675,7 +585,7 @@ TR::Instruction *OMR::Power::Linkage::flushArguments(TR::Instruction *cursor)

case TR::Float:
case TR::Double:
if (hasToStoreToStack &&
if (hasToStoreOrLoadStack &&
numFloatArgs<properties.getNumFloatArgRegs())
{
argRegister = machine->getRealRegister(properties.getFloatArgumentRegister(numFloatArgs));
Expand All @@ -685,24 +595,26 @@ TR::Instruction *OMR::Power::Linkage::flushArguments(TR::Instruction *cursor)

if (paramCursor->getDataType() == TR::Float)
{
op = TR::InstOpCode::stfs; length = 4;
op = flush ? TR::InstOpCode::stfs : op = TR::InstOpCode::lfs; length = 4;
}
else
{
op = TR::InstOpCode::stfd; length = 8;
op = flush ? TR::InstOpCode::stfd : op = TR::InstOpCode::lfd; length = 8;
}

cursor = generateMemSrc1Instruction(self()->cg(), op, firstNode,
cursor = flush ? generateMemSrc1Instruction(self()->cg(), op, firstNode,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, length, self()->cg()),
argRegister, cursor);
argRegister, cursor):
generateTrg1MemInstruction(self()->cg(), op, firstNode, argRegister,
new (self()->trHeapMemory()) TR::MemoryReference(stackPtr, offset, length, self()->cg()), cursor);
}
numFloatArgs++;
break;
}
paramCursor = paramIterator.getNext();
}
return(cursor);
}
}

TR::Register *OMR::Power::Linkage::pushIntegerWordArg(TR::Node *child)
{
Expand Down
4 changes: 2 additions & 2 deletions compiler/p/codegen/OMRLinkage.hpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -372,8 +372,8 @@ class OMR_EXTENSIBLE Linkage : public OMR::Linkage
virtual TR::MemoryReference *getOutgoingArgumentMemRef(int32_t argSize, TR::Register *argReg, TR::InstOpCode::Mnemonic opCode, TR::PPCMemoryArgument &memArg, uint32_t len);
virtual TR::Instruction *saveArguments(TR::Instruction *cursor, bool fsd=false, bool saveOnly=false);
virtual TR::Instruction *saveArguments(TR::Instruction *cursor, bool fsd, bool saveOnly, List<TR::ParameterSymbol> &parmList);
virtual TR::Instruction *loadUpArguments(TR::Instruction *cursor);
virtual TR::Instruction *flushArguments(TR::Instruction *cursor);
//flush arugment if flush = true. Load argument if flush = false
virtual TR::Instruction *flushOrloadUpArguments(TR::Instruction *cursor, bool flush);
virtual void setParameterLinkageRegisterIndex(TR::ResolvedMethodSymbol *method);
TR::Register *pushIntegerWordArg(TR::Node *child);

Expand Down

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