[dv] Remove do_tl_err argument from run_seq_with_rand_reset_vseq

This is set to 1 at all the callsites, so simplify things by getting
rid of the unused argument.

Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>

hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv

@@ -700,12 +700,11 @@ class cip_base_vseq #(
   virtual task rand_reset_eor_clean_up();
   endtask
 
-  // Run the given sequence and possibly a TL errors vseq (if do_tl_err is set). Suddenly inject a
-  // reset after at most reset_delay_bound cycles. When we come out of reset, check all CSR values
-  // to ensure they are the documented reset values.
+  // Run the given sequence together with a TL errors vseq. Suddenly inject a reset after at most
+  // reset_delay_bound cycles. When we come out of reset, check all CSR values to ensure they are
+  // the documented reset values.
   virtual task run_seq_with_rand_reset_vseq(uvm_sequence seq,
                                             int          num_times = 1,
-                                            bit          do_tl_err = 1,
                                             uint         reset_delay_bound = 10_000_000);
     `DV_CHECK_FATAL(seq != null)
     `uvm_info(`gfn, $sformatf("running run_seq_with_rand_reset_vseq for sequence %s",
@@ -718,16 +717,14 @@ class cip_base_vseq #(
                                 i, num_times), UVM_LOW)
       // Arbitration: requests at highest priority granted in FIFO order, so that we can predict
       // results for many non-blocking accesses
-      if (do_tl_err) p_sequencer.tl_sequencer_h.set_arbitration(UVM_SEQ_ARB_STRICT_FIFO);
+      p_sequencer.tl_sequencer_h.set_arbitration(UVM_SEQ_ARB_STRICT_FIFO);
       fork
         begin: isolation_fork
           fork : run_test_seqs
             begin : seq_wo_reset
               fork
                 begin : tl_err_seq
-                  if (do_tl_err) begin
-                    run_tl_errors_vseq(.num_times($urandom_range(10, 1000)), .do_wait_clk(1'b1));
-                  end
+                  run_tl_errors_vseq(.num_times($urandom_range(10, 1000)), .do_wait_clk(1'b1));
                 end
                 begin : run_stress_seq
                   dv_base_vseq #(RAL_T, CFG_T, COV_T, VIRTUAL_SEQUENCER_T) dv_vseq;
@@ -1037,8 +1034,7 @@ class cip_base_vseq #(
     // injecting a reset. Since the IP block is otherwise quiescent, we only really care about what
     // point in a TL transaction the reset occurs. Each TL transaction takes roughly 10 cycles, so
     // there's no need to wait longer than 1000 cycles (which would be ~100 TL transactions).
-    run_seq_with_rand_reset_vseq(.seq(cip_seq), .num_times(num_times), .do_tl_err(1),
-                                 .reset_delay_bound(1000));
+    run_seq_with_rand_reset_vseq(.seq(cip_seq), .num_times(num_times), .reset_delay_bound(1000));
   endtask
 
   // TLUL mask must be contiguous, e.g. 'b1001, 'b1010 aren't allowed