[dv] Remove default value for wait_to_issue_reset argument

Every callsite for this task passes a value for the argument. Signed-off-by: Rupert Swarbrick <rswarbrick@lowrisc.org>
vsukhoml · May 31, 2024 · 7d8ace2 · 7d8ace2
1 parent 2a42ee8
commit 7d8ace2
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv b/hw/dv/sv/cip_lib/seq_lib/cip_base_vseq.sv
@@ -787,7 +787,7 @@ class cip_base_vseq #(
   // accesses can also be set by derived classes for special cases. If the wait doesn't clear
   // something is probably wrong: perhaps some loop sending CSR transactions is missing a
   // break if stop_transaction_generators() is set.
-  virtual task wait_to_issue_reset(uint reset_delay_bound = 10_000_000);
+  virtual task wait_to_issue_reset(uint reset_delay_bound);
     int cycles_with_no_accesses = 0;
     int cycles_waited;
 

diff --git a/hw/ip/hmac/dv/env/seq_lib/hmac_common_vseq.sv b/hw/ip/hmac/dv/env/seq_lib/hmac_common_vseq.sv
@@ -28,7 +28,7 @@ class hmac_common_vseq extends hmac_base_vseq;
     run_common_vseq_wrapper(num_trans);
   endtask : body
 
-  virtual task wait_to_issue_reset(uint reset_delay_bound = 10_000_000);
+  virtual task wait_to_issue_reset(uint reset_delay_bound);
     `DV_CHECK_MEMBER_RANDOMIZE_FATAL(trig_rst_during_hash)
 
     if (trig_rst_during_hash) begin