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Pull requests: verilog-to-routing/vtr-verilog-to-routing
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[WIP] Tileable Routing Resource Graph Builder
build
Build system
docs
Documentation
external_libs
infra
Project Infrastructure
lang-cpp
C/C++ code
lang-hdl
Hardware Description Language (Verilog/VHDL)
lang-make
CMake/Make code
lang-netlist
lang-python
Python code
lang-shell
Shell scripts (bash etc.)
libarchfpga
Library for handling FPGA Architecture descriptions
liblog
libpugiutil
libvtrutil
Odin
Odin II Logic Synthesis Tool: Unsorted item
Parmys
scripts
Utility & Infrastructure scripts
VPR
VPR FPGA Placement & Routing Tool
#2135
opened Aug 16, 2022 by
tangxifan
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updated Jun 11, 2025
7 of 19 tasks
WIP: Subtraction Fix in ODIN
lang-cpp
C/C++ code
Odin
Odin II Logic Synthesis Tool: Unsorted item
Parmys
#2307
opened May 8, 2023 by
navidjafarof
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updated Feb 14, 2024
1 of 7 tasks
WIP: Implement inout support into ODIN II
lang-cpp
C/C++ code
lang-hdl
Hardware Description Language (Verilog/VHDL)
lang-shell
Shell scripts (bash etc.)
Odin
Odin II Logic Synthesis Tool: Unsorted item
scripts
Utility & Infrastructure scripts
tests
#1292
opened May 1, 2020 by
djns99
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updated Jan 24, 2023
2 of 6 tasks
Upgrade the Yosys+Odin-II Front-end
Odin
Odin II Logic Synthesis Tool: Unsorted item
Yosys+Odin-II
The Yosys+Odin-II synthesizer: the Yosys coarse-grained Tcl script and Odin-II partial mapping flow
#2148
opened Aug 29, 2022 by
sdamghan
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updated Oct 5, 2022
2 of 7 tasks
WIP: clang-tidy fixes around const std::string references.
ABC
ABC Logic Optimization & Technology Mapping Tool
external_libs
libarchfpga
Library for handling FPGA Architecture descriptions
libpugiutil
libvtrutil
Odin
Odin II Logic Synthesis Tool: Unsorted item
VPR
VPR FPGA Placement & Routing Tool
#1764
opened Jun 3, 2021 by
mithro
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updated Jun 17, 2021
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