more tweaks to pass gate level sims

e2e/Makefile

@@ -23,7 +23,9 @@ TOOLS_CONF			?= configs-tool/$(tools).yml
 # design-specific overrides of default configs
 DESIGN_CONF			?= configs-design/$(design)/common.yml
 DESIGN_TECH_CONF	?= configs-design/$(design)/$(tech).yml
-SIM_CONF			?= configs-design/$(design)/sim-rtl.yml
+SIM_CONF			?= $(if $(findstring sim-syn,$(MAKECMDGOALS)), configs-design/$(design)/sim-syn.yml, \
+					   $(if $(findstring sim-par,$(MAKECMDGOALS)), configs-design/$(design)/sim-par.yml, \
+					   configs-design/$(design)/sim-rtl.yml))
 POWER_CONF			?= $(if $(findstring power-rtl,$(MAKECMDGOALS)), configs-design/$(design)/power-rtl-$(tech).yml, \
 					   $(if $(findstring power-syn,$(MAKECMDGOALS)), configs-design/$(design)/power-syn-$(tech).yml,))
 
@@ -41,7 +43,4 @@ build: $(HAMMER_D_MK)
 $(HAMMER_D_MK):
 	hammer-vlsi --obj_dir $(OBJ_DIR) -e $(ENV_YML) $(HAMMER_EXTRA_ARGS) build
 
-sim-syn: override SIM_CONF = configs-design/$(design)/sim-syn.yml
-sim-par: override SIM_CONF = configs-design/$(design)/sim-par.yml
-
 -include $(HAMMER_D_MK)

e2e/configs-design/gcd/asap7.yml

@@ -3,6 +3,10 @@ vlsi.inputs.clocks: [
   {name: "clk", period: "5ns", uncertainty: "0.1ns"}
 ]
 
+sim.inputs:
+  defines: ['CLOCK_PERIOD=5']
+  defines_meta: 'append'
+
 # Placement Constraints
 vlsi.inputs.placement_constraints:
   - path: "gcd"
@@ -22,8 +26,3 @@ vlsi.inputs.pin.generate_mode: semi_auto
 vlsi.inputs.pin.assignments: [
   {pins: "*", layers: ["M5"], side: "bottom"}
 ]
-
-vlsi.inputs.delays: [
-  {name: "in", clock: "clk", delay: "1", direction: "input"},
-  {name: "out", clock: "clk", delay: "2", direction: "output"}
-]

e2e/configs-design/gcd/sim-par.yml

@@ -7,8 +7,6 @@ sim.inputs:
   input_files: ['src/gcd_tb.v']
   input_files_meta: append
   level: "par"
-  defines: ['CLOCK_PERIOD=1']
-  defines_meta: 'append'
   options: ['-timescale=1ns/10ps']
   options_meta: append
   timing_annotated: false

e2e/configs-design/gcd/sim-rtl.yml

@@ -5,9 +5,9 @@ sim.inputs:
   tb_dut: gcd_dut
   tb_name: "gcd_tb"
   input_files: ['src/gcd.v', 'src/gcd_tb.v']
-  options: ['-timescale=1ns/10ps']
-  options_meta: append
   defines: ['CLOCK_PERIOD=1']
   defines_meta: 'append'
+  options: ['-timescale=1ns/10ps']
+  options_meta: append
 
 # sim.inputs.execute_sim: false

e2e/configs-design/gcd/sim-syn.yml

@@ -7,8 +7,6 @@ sim.inputs:
   input_files: ['src/gcd_tb.v']
   input_files_meta: append
   level: "syn"
-  defines: ['CLOCK_PERIOD=1']
-  defines_meta: 'append'
   options: ['-timescale=1ns/10ps']
   options_meta: append
   timing_annotated: true

e2e/configs-design/gcd/sky130.yml

@@ -3,6 +3,10 @@ vlsi.inputs.clocks: [
   {name: "clk", period: "10ns", uncertainty: "0.1ns"}
 ]
 
+sim.inputs:
+  defines: ['CLOCK_PERIOD=10']
+  defines_meta: 'append'
+
 # Placement Constraints
 vlsi.inputs.placement_constraints:
   - path: "gcd"
@@ -47,8 +51,3 @@ vlsi.inputs.pin.generate_mode: semi_auto
 vlsi.inputs.pin.assignments: [
   {pins: "*", layers: ["met4"], side: "bottom"}
 ]
-
-vlsi.inputs.delays: [
-  {name: "in", clock: "clk", delay: "1", direction: "input"},
-  {name: "out", clock: "clk", delay: "2", direction: "output"}
-]

e2e/configs-design/test/asap7.yml

@@ -3,6 +3,10 @@ vlsi.inputs.clocks: [
   {name: "clock", period: "5ns", uncertainty: "0.1ns"}
 ]
 
+sim.inputs:
+  defines: ['CLOCK_PERIOD=5']
+  defines_meta: 'append'
+
 # Tool options.
 vlsi.inputs.placement_constraints:
   - path: "pass"

e2e/configs-design/test/joules.yml

@@ -8,4 +8,4 @@ power.inputs.tb_name: "pass_tb"
 power.inputs.tb_dut: "pass_0"
 power.inputs.waveforms: ["path/to/waveforem"]
 
-power.inputs.power_spec: "auto"
+power.inputs.power_spec: "auto"

e2e/configs-design/test/power-rtl-asap7.yml

@@ -31,4 +31,4 @@ sim.inputs:
 # clock period for Joules fast-synth
 vlsi.inputs.clocks: [
   {name: "clock", period: "1ns", uncertainty: "10ps"}
-]
+]

e2e/configs-design/test/power-rtl-sky130.yml

@@ -31,4 +31,4 @@ sim.inputs:
 # clock period for Joules fast-synth
 vlsi.inputs.clocks: [
   {name: "clock", period: "5ns", uncertainty: "100ps"}
-]
+]

e2e/configs-design/test/sim-par.yml

@@ -7,8 +7,6 @@ sim.inputs:
   input_files: ['src/pass_tb.v']
   input_files_meta: append
   level: "par"
-  defines: ['CLOCK_PERIOD=1']
-  defines_meta: 'append'
   options: ['-timescale=1ns/10ps']
   options_meta: append
   timing_annotated: false

e2e/configs-design/test/sim-syn.yml

@@ -7,8 +7,6 @@ sim.inputs:
   input_files: ['src/pass_tb.v']
   input_files_meta: append
   level: "syn"
-  defines: ['CLOCK_PERIOD=1']
-  defines_meta: 'append'
   options: ['-timescale=1ns/10ps']
   options_meta: append
   timing_annotated: true

e2e/configs-design/test/sky130.yml

@@ -3,6 +3,10 @@ vlsi.inputs.clocks: [
   {name: "clock", period: "10ns", uncertainty: "0.1ns"}
 ]
 
+sim.inputs:
+  defines: ['CLOCK_PERIOD=10']
+  defines_meta: 'append'
+
 # Placement Constraints
 vlsi.inputs.placement_constraints:
   - path: "pass"
@@ -17,30 +21,6 @@ vlsi.inputs.placement_constraints:
       top: 10
       bottom: 10
 
-# Power Straps
-par.power_straps_mode: generate
-par.generate_power_straps_method: by_tracks
-par.blockage_spacing: 40.0
-par.blockage_spacing_top_layer: met4
-par.generate_power_straps_options:
-  by_tracks:
-    strap_layers:
-      - met4
-      - met5
-    pin_layers:
-      - met5
-    blockage_spacing_met2: 4.0
-    blockage_spacing_met4: 2.0
-    blockage_spacing_met4: 2.0
-    track_width: 3
-    track_width_met5: 1
-    track_spacing: 5
-    track_start: 10
-    track_start_met5: 1
-    power_utilization: 0.1
-    power_utilization_met4: 0.1
-    power_utilization_met5: 0.1
-
 # Pin placement constraints
 vlsi.inputs.pin_mode: generated
 vlsi.inputs.pin.generate_mode: semi_auto

e2e/configs-tech/sky130.yml

@@ -8,4 +8,10 @@ vlsi.inputs.pin_mode: generated
 vlsi.inputs.pin.generate_mode: semi_auto
 vlsi.inputs.pin.assignments: [
   {pins: "*", layers: ["met4"], side: "bottom"}
-]
+]
+
+# TODO: _meta configs aren't propagated into action output configs, so tech/tool plugin _meta's are lost
+# ex. flags below are lost during sim-syn/par (but not sim-rtl)
+sim.inputs:
+  defines: ["FUNCTIONAL", "UNIT_DELAY=#1"]
+  defines_meta: 'append'

e2e/src/pass_tb.v

@@ -47,6 +47,7 @@ module pass_tb;
             $display("***Test Failed***");
         end
 
+        $display("***TEST COMPLETE***");
         $fsdbDumpoff;
         $finish;
 

hammer/config/defaults.yml

@@ -846,15 +846,30 @@ power.inputs:
   # type: List[PowerReport]
   # PowerReport struct members:
   # waveform_path (str) - Path to the waveform for the report
-  # module (str) - Optional. the path to the module to report power for (default here is the Chipyard top level)
-  # levels (int) - Optional. the number of levels in the design hierachy to report
-  # start_time (str) - Optional. The start time of the power report in the waveform
-  # end_time (str) - Optional. The end time of the power report in the waveform
+  # inst (str) - Optional. Hierarchical or leaf instance to report power for
+  # module (str) - Optional. The module to report power for (default here is the Chipyard top level). All instances of this module are used for the power report.
+  # levels (int) - Optional. The number of levels in the design hierachy to report
+  # start_time (TimeValue) - Optional. The start time of the power report in the waveform
+  # end_time (TimeValue) - Optional. The end time of the power report in the waveform
+  # interval_size (TimeValue) - Optional. Divide the stimulus into frames of this size
   # toggle_signal (str) - Optional. Path to the signal to generate report windows based on toggles
-  # num_toggles (int) - Optional (must be specified if num_toggles is specified). The number of toggles of the toggle_signal for each frame to report power
-  # frame_count (int) - Optional. The number of frames to report the power for
-  # report_name (str) - Optional. Name of the power report
-  # example: report_configs: [{waveform_path: "/path/to/fsdb", module: "chiptop", levels:3, start_time: "0ns", end_time: "1ns", toggle_signal:"/ChipTop/clock", num_toggles:1, frame_count:1000, report_name: "my_fsdb_report"}]
+  # num_toggles (int) - Optional (must be specified if toggle_signal is specified). The number of toggles of the toggle_signal for each frame to report power
+  # frame_count (int) - Optional. The number of frames to report the power for. Default: 1
+  # report_name (str) - Optional. Name of the power report, but MUST NOT contain file extension.
+  #     If an absolute path is provided, this is used as the path (plus file extension).
+  #     If a relative path or just the filename is provided, output file will be saved to <power-rundir>/<output_format-type>/<report_name>.<ext>
+  #     Default: waveform file name
+  # output_formats (List[str]) - Optional. Report types to generate. Default: ["report"]
+  #   Valid options are:
+  #     "report" - average power report (*.rpt), default
+  #     "plot_profile" - power profile over time, requires frame-based analysis (*.png, *.png.data)
+  #     "write_profile" - profiles all power types on all categories for all the sub-hierarchies for a given design instance (*.fsdb)
+  #     "profile" - run plot_profile + dump_profile
+  #     "all" - generate all of the above report formats
+
+  # examples:
+  #   report_configs: [{waveform_path: "/path/to/fsdb", module: "chiptop", levels:3, start_time: "0ns", end_time: "1ns", toggle_signal:"/ChipTop/clock", num_toggles:1, frame_count:1000, report_name: "my_fsdb_report"}]
+  #   report_configs: [{waveform_path: "/path/to/fsdb", inst: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile", interval_size: "1ns", output_formats: ["plot_profile"]}]
 
   level: "rtl" # Power analysis mode for different levels of the VLSI flow
   # Valid options are:

hammer/power/joules/__init__.py

@@ -368,13 +368,13 @@ def report_power(self) -> bool:
                 # NOTE: including the '-frames $frames ' argument results in this Joules error: "Error: Cannot specify frame#0 if other frames are specified with -frames.""
                 # NOTE: we don't include levels_str here bc category is total power anyways
                 self.block_append(f"plot_power_profile -stims {stim_alias} {inst_str} {module_str} -by_category {{total}} -types {{total}} -unit mW -format png -out {report_path}.png")
-            if {'dump_profile','profile','all'} & output_formats:
+            if {'write_profile','profile','all'} & output_formats:
                 report_path = report_name
                 if not report_path.startswith('/'):
-                    save_dir = os.path.join(self.run_dir, 'dump_profile')
+                    save_dir = os.path.join(self.run_dir, 'write_profile')
                     os.makedirs(save_dir, exist_ok=True)
                     report_path = os.path.join(save_dir, report_path)
-                verbose_append(f"dump_power_profile -stims {stim_alias} -root [get_insts -rtl_type hier] {levels_str} -unit mW -format fsdb -out {report_path}")
+                verbose_append(f"write_power_profile -stims {stim_alias} -root [get_insts -rtl_type hier] {levels_str} -unit mW -format fsdb -out {report_path}")
 
         saifs = self.get_setting("power.inputs.saifs")
         for saif in saifs: