Merge pull request #21 from ucb-bar/clusters

Update to latest Rocket-chip API
ucb-bar · Jan 11, 2024 · 777f289 · 777f289
2 parents c44c12b + 9d1c106
commit 777f289
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Showing 2 changed files with 11 additions and 8 deletions.
diff --git a/src/main/scala/cva6/CVA6Tile.scala b/src/main/scala/cva6/CVA6Tile.scala
@@ -95,7 +95,7 @@ case class CVA6TileAttachParams(
 // TODO: BTBParams, DCacheParams, ICacheParams are incorrect in DTB... figure out defaults in CVA6 and put in DTB
 case class CVA6TileParams(
   name: Option[String] = Some("cva6_tile"),
-  hartId: Int = 0,
+  tileId: Int = 0,
   trace: Boolean = false,
   val core: CVA6CoreParams = CVA6CoreParams()
 ) extends InstantiableTileParams[CVA6Tile]
@@ -107,9 +107,11 @@ case class CVA6TileParams(
   val dcache: Option[DCacheParams] = Some(DCacheParams())
   val icache: Option[ICacheParams] = Some(ICacheParams())
   val clockSinkParams: ClockSinkParameters = ClockSinkParameters()
-  def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): CVA6Tile = {
+  def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): CVA6Tile = {
     new CVA6Tile(this, crossing, lookup)
   }
+  val baseName = name.getOrElse("cva6_tile")
+  val uniqueName = s"${baseName}_$tileId"
 }
 
 class CVA6Tile private(
@@ -125,10 +127,10 @@ class CVA6Tile private(
    * Setup parameters:
    * Private constructor ensures altered LazyModule.p is used implicitly
    */
-  def this(params: CVA6TileParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
+  def this(params: CVA6TileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
     this(params, crossing.crossingType, lookup, p)
 
-  val intOutwardNode = IntIdentityNode()
+  val intOutwardNode = None
   val slaveNode = TLIdentityNode()
   val masterNode = visibilityNode
 
@@ -148,7 +150,7 @@ class CVA6Tile private(
   }
 
   ResourceBinding {
-    Resource(cpuDevice, "reg").bind(ResourceAddress(staticIdForMetadataUseOnly))
+    Resource(cpuDevice, "reg").bind(ResourceAddress(tileId))
   }
 
  override def makeMasterBoundaryBuffers(crossing: ClockCrossingType)(implicit p: Parameters) = crossing match {

diff --git a/src/main/scala/cva6/ConfigMixins.scala b/src/main/scala/cva6/ConfigMixins.scala
@@ -34,18 +34,19 @@ class WithToFromHostCaching extends Config((site, here, up) => {
  *
  * @param n amount of tiles to duplicate
  */
-class WithNCVA6Cores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => {
+class WithNCVA6Cores(n: Int = 1) extends Config((site, here, up) => {
   case TilesLocated(InSubsystem) => {
     val prev = up(TilesLocated(InSubsystem), site)
-    val idOffset = overrideIdOffset.getOrElse(prev.size)
+    val idOffset = up(NumTiles)
     (0 until n).map { i =>
       CVA6TileAttachParams(
-        tileParams = CVA6TileParams(hartId = i + idOffset),
+        tileParams = CVA6TileParams(tileId = i + idOffset),
         crossingParams = RocketCrossingParams()
       )
     } ++ prev
   }
   case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 8)
   case XLen => 64
+  case NumTiles => up(NumTiles) + n
 })