Local FPGA Support - Arty/VCU118

.circleci/README.md

@@ -34,11 +34,19 @@ Here the key is built from a string where the `checksum` portion converts the fi
 This directory contains all the collateral for the Chipyard CI to work.
 The following is included:
 
-    `build-toolchains.sh` # build either riscv-tools or esp-tools
-    `create-hash.sh`      # create hashes of riscv-tools/esp-tools so circleci caching can work
-    `do-rtl-build.sh`     # use verilator to build a sim executable (remotely)
-    `config.yml`          # main circleci config script to enumerate jobs/workflows
-    `defaults.sh`         # default variables used
+    `build-toolchains.sh`        # build either riscv-tools or esp-tools
+    `create-hash.sh`             # create hashes of riscv-tools/esp-tools so circleci caching can work
+    `do-rtl-build.sh`            # use verilator to build a sim executable (remotely)
+    `config.yml`                 # main circleci config script to enumerate jobs/workflows
+    `defaults.sh`                # default variables used
+    `check-commit.sh`            # check that submodule commits are valid
+    `build-extra-tests.sh`       # build default chipyard tests located in tests/
+    `clean-old-files.sh`         # clean up build server files
+    `do-fpga-rtl-build.sh`       # similar to `do-rtl-build` but using fpga/
+    `install-verilator.sh`       # install verilator on build server
+    `run-firesim-scala-tests.sh` # run firesim scala tests
+    `run-tests.sh                # run tests for a specific set of designs
+    `images/`                    # docker image used in CI
 
 How things are setup for Chipyard
 ---------------------------------

.circleci/check-commit.sh

@@ -120,6 +120,10 @@ dir="vlsi"
 branches=("master")
 search
 
+submodules=("fpga-shells")
+dir="fpga"
+branches=("master")
+search
 
 # turn off verbose printing to make this easier to read
 set +x

.circleci/config.yml

@@ -82,12 +82,15 @@ commands:
             build-script:
                 type: string
                 default: "do-rtl-build.sh"
+            build-type:
+                type: string
+                default: "sim"
         steps:
             - setup-tools:
                 tools-version: "<< parameters.tools-version >>"
             - run:
                 name: Building << parameters.group-key >> subproject using Verilator
-                command: .circleci/<< parameters.build-script >> << parameters.group-key >>
+                command: .circleci/<< parameters.build-script >> << parameters.group-key >> << parameters.build-type >>
                 no_output_timeout: << parameters.timeout >>
             - save_cache:
                 key: << parameters.group-key >>-{{ .Branch }}-{{ .Revision }}
@@ -368,6 +371,12 @@ jobs:
                 project-key: "firesim-multiclock"
                 run-script: "run-firesim-scala-tests.sh"
                 timeout: "20m"
+    prepare-chipyard-fpga:
+        executor: main-env
+        steps:
+            - prepare-rtl:
+                group-key: "group-fpga"
+                build-type: "fpga"
 
 # Order and dependencies of jobs to run
 workflows:
@@ -507,4 +516,8 @@ workflows:
                     - install-verilator
                     - build-extra-tests
 
+            # Prepare the fpga builds (just Verilog)
+            - prepare-chipyard-fpga:
+                requires:
+                    - install-riscv-toolchain
 

.circleci/defaults.sh

@@ -33,6 +33,7 @@ REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install
 REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard
 REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator
 REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim
+REMOTE_FPGA_DIR=$REMOTE_CHIPYARD_DIR/fpga
 REMOTE_JAVA_OPTS="-Xmx10G -Xss8M"
 # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI
 REMOTE_SBT_OPTS="-Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot"
@@ -53,6 +54,7 @@ grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spifl
 grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
 grouping["group-tracegen"]="tracegen tracegen-boom"
 grouping["group-other"]="icenet testchipip"
+grouping["group-fpga"]="arty vcu118"
 
 # key value store to get the build strings
 declare -A mapping
@@ -83,3 +85,6 @@ mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Test
 mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests"
 mapping["icenet"]="SUB_PROJECT=icenet"
 mapping["testchipip"]="SUB_PROJECT=testchipip"
+
+mapping["arty"]="SUB_PROJECT=arty verilog"
+mapping["vcu118"]="SUB_PROJECT=vcu118 verilog"

.circleci/do-rtl-build.sh

@@ -1,7 +1,11 @@
 #!/bin/bash
 
 # create the different verilator builds
-# argument is the make command string
+# usage:
+#   do-rtl-build.sh <make command string> sim
+#     run rtl build for simulations and copy back results
+#   do-rtl-build.sh <make command string> fpga
+#     run rtl build for fpga and don't copy back results
 
 # turn echo on and error on earliest command
 set -ex
@@ -15,6 +19,7 @@ trap clean EXIT
 
 cd $LOCAL_CHIPYARD_DIR
 ./scripts/init-submodules-no-riscv-tools.sh
+./scripts/init-fpga.sh
 
 # set stricthostkeychecking to no (must happen before rsync)
 run "echo \"Ping $SERVER\""
@@ -50,9 +55,19 @@ else
     copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR
 fi
 
+# choose what make dir to use
+case $2 in
+    "sim")
+        REMOTE_MAKE_DIR=$REMOTE_SIM_DIR
+        ;;
+    "fpga")
+        REMOTE_MAKE_DIR=$REMOTE_FPGA_DIR
+        ;;
+esac
+
 # enter the verilator directory and build the specific config on remote server
 run "export RISCV=\"$TOOLS_DIR\"; \
-     make -C $REMOTE_SIM_DIR clean;"
+     make -C $REMOTE_MAKE_DIR clean;"
 
 read -a keys <<< ${grouping[$1]}
 
@@ -64,11 +79,14 @@ do
          export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \
          export VERILATOR_ROOT=\"$REMOTE_VERILATOR_DIR\"; \
          export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \
-         make -j$REMOTE_MAKE_NPROC -C $REMOTE_SIM_DIR FIRRTL_LOGLEVEL=info JAVA_OPTS=\"$REMOTE_JAVA_OPTS\" SBT_OPTS=\"$REMOTE_SBT_OPTS\" ${mapping[$key]}"
+         make -j$REMOTE_MAKE_NPROC -C $REMOTE_MAKE_DIR FIRRTL_LOGLEVEL=info JAVA_OPTS=\"$REMOTE_JAVA_OPTS\" SBT_OPTS=\"$REMOTE_SBT_OPTS\" ${mapping[$key]}"
 done
 
 run "rm -rf $REMOTE_CHIPYARD_DIR/project"
 
-# copy back the final build
-mkdir -p $LOCAL_CHIPYARD_DIR
-copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR
+# choose to copy back results
+if [ $2 = "sim" ]; then
+    # copy back the final build
+    mkdir -p $LOCAL_CHIPYARD_DIR
+    copy $SERVER:$REMOTE_CHIPYARD_DIR/ $LOCAL_CHIPYARD_DIR
+fi

.gitmodules

@@ -131,3 +131,6 @@
 [submodule "generators/riscv-sodor"]
 	path = generators/riscv-sodor
 	url = https://github.com/ucb-bar/riscv-sodor.git
+[submodule "fpga/fpga-shells"]
+	path = fpga/fpga-shells
+	url = https://github.com/sifive/fpga-shells.git

LICENSE.SiFive

@@ -0,0 +1,202 @@
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build.sbt

@@ -311,3 +311,11 @@ lazy val firechip = (project in file("generators/firechip"))
     testGrouping in Test := isolateAllTests( (definedTests in Test).value ),
     testOptions in Test += Tests.Argument("-oF")
   )
+lazy val fpga_shells = (project in file("./fpga/fpga-shells"))
+  .dependsOn(rocketchip, sifive_blocks)
+  .settings(libraryDependencies ++= rocketLibDeps.value)
+  .settings(commonSettings)
+
+lazy val fpga_platforms = (project in file("./fpga"))
+  .dependsOn(chipyard, fpga_shells)
+  .settings(commonSettings)

common.mk

@@ -61,7 +61,7 @@ include $(base_dir)/tools/dromajo/dromajo.mk
 # Returns a list of files in directory $1 with file extension $2.
 lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -print 2> /dev/null)
 
-SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell)
+SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell fpga/fpga-shells fpga/src)
 SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala)
 VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v)
 # This assumes no SBT meta-build sources