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Unify htif implementation with firesim #683

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merged 3 commits into from
Oct 12, 2020
Merged

Unify htif implementation with firesim #683

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d71c3b6
Unify htif implementation with firesim
jerryz123 Oct 2, 2020
25129c2
Add testchip_fesvr to uncondtionally used resources
jerryz123 Oct 2, 2020
0c46ed1
Rename testchip_fesvr to testchip_tsi
jerryz123 Oct 9, 2020
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Rename testchip_fesvr to testchip_tsi
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@jerryz123
jerryz123 committed Oct 9, 2020
commit 0c46ed167633ebe948ac746f9e0eccd9ab69b361
2 changes: 1 addition & 1 deletion generators/testchipip
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Submodule testchipip updated 4 files
+3 −3 src/main/resources/testchipip/csrc/SimSerial.cc
+4 −4 src/main/resources/testchipip/csrc/testchip_tsi.cc
+5 −5 src/main/resources/testchipip/csrc/testchip_tsi.h
+2 −2 src/main/scala/SerialAdapter.scala
4 changes: 2 additions & 2 deletions generators/utilities/src/main/scala/Simulator.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -83,8 +83,8 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
}
def resources(sim: Simulator): Seq[String] = Seq(
"/testchipip/csrc/SimSerial.cc",
"/testchipip/csrc/testchip_fesvr.cc",
"/testchipip/csrc/testchip_fesvr.h",
"/testchipip/csrc/testchip_tsi.cc",
"/testchipip/csrc/testchip_tsi.h",
"/testchipip/csrc/SimDRAM.cc",
"/testchipip/csrc/mm.h",
"/testchipip/csrc/mm.cc",
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2 changes: 1 addition & 1 deletion sims/firesim
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Submodule firesim updated 5 files
+5 −5 sim/firesim-lib/src/main/cc/bridges/serial.cc
+2 −2 sim/firesim-lib/src/main/cc/bridges/serial.h
+11 −11 sim/firesim-lib/src/main/cc/fesvr/firesim_tsi.cc
+7 −7 sim/firesim-lib/src/main/cc/fesvr/firesim_tsi.h
+2 −2 sim/src/main/makefrag/firesim/Makefrag