Add RANDOM_SEED variable to set random init for VCS and Verilator simulations #629
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jerryz123
commented
Jul 17, 2020
| @@ -47,13 +47,11 @@ VCS_OPTS = -notice -line $(VCS_CC_OPTS) $(VCS_NONCC_OPTS) $(VCS_DEFINE_OPTS) $(E | |||
| # vcs simulator rules | |||
| ######################################################################################### | |||
| $(sim): $(sim_vsrcs) $(sim_common_files) $(dramsim_lib) $(EXTRA_SIM_REQS) | |||
| rm -rf csrc && $(VCS) $(VCS_OPTS) -o $@ \ | |||
| -debug_pp | |||
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-debug_pp is already defined in VCS_OPTS
colinschmidt
requested changes
Jul 19, 2020
| @@ -29,6 +29,7 @@ sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG) | |||
| sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug | |||
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| WAVEFORM_FLAG=-v$(sim_out_name).vcd | |||
| SEED_FLAG=+verilator+seed+I$(RANDOM_SEED) | |||
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Good thing we added support for these flags 😝
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I'm with Colin on this. We should just print the seed if we don't already.
…On Sun, Jul 19, 2020 at 4:23 PM Jerry Zhao ***@***.***> wrote:
***@***.**** commented on this pull request.
------------------------------
In variables.mk
<#629 (comment)>:
> @@ -167,6 +167,7 @@ PERMISSIVE_OFF=+permissive-off
BINARY ?=
override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles)
VERBOSE_FLAGS ?= +verbose
+RANDOM_SEED ?= 1
The current behavior in VCS uses 1 as the seed for every run. I think
having default be deterministic makes more sense, otherwise it will always
be annoying to reproduce some non-determinism-induced bug.
Users looking for randomness can just set RANDOM_SEED=$RANDOM
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The seed is already printed in the |
Merged
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Setting
RANDOM_SEEDnow lets you control the random seed for VCS and Verilator. LeavingRANDOM_SEEDunset results in randomly generated seed.Related issue:
Type of change: new feature
Impact: software change
Release Notes