Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Emit htif node in device tree #607

Merged
merged 1 commit into from
Jun 22, 2020
Merged
Changes from all commits
Commits
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
25 changes: 23 additions & 2 deletions generators/chipyard/src/main/scala/Subsystem.scala
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ import chisel3.internal.sourceinfo.{SourceInfo}

import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug}
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt}
import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree}
Expand All @@ -24,7 +24,7 @@ import freechips.rocketchip.amba.axi4._
import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams}
import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams}

import testchipip.{DromajoHelper}
import testchipip.{DromajoHelper, CanHavePeripherySerial, SerialKey}

trait HasChipyardTiles extends HasTiles
with CanHavePeripheryPLIC
Expand Down Expand Up @@ -87,8 +87,29 @@ trait HasChipyardTilesModuleImp extends HasTilesModuleImp
val outer: HasChipyardTiles
}

trait CanHaveHTIF { this: BaseSubsystem =>
// Advertise HTIF if system can communicate with fesvr
if (this match {
case _: CanHavePeripherySerial if p(SerialKey) => true
case _: HasPeripheryDebug if p(ExportDebug).protocols.nonEmpty => true
case _ => false
}) {
ResourceBinding {
val htif = new Device {
def describe(resources: ResourceBindings): Description = {
val compat = resources("compat").map(_.value)
Description("htif", Map(
"compatible" -> compat))
}
}
Resource(htif, "compat").bind(ResourceString("ucb,htif0"))
}
}
}

class Subsystem(implicit p: Parameters) extends BaseSubsystem
with HasChipyardTiles
with CanHaveHTIF
{
override lazy val module = new SubsystemModuleImp(this)

Expand Down