Bump toolchains/riscv-tools/riscv-isa-sim from 2890ea7 to 6f28e4b
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Bumps [toolchains/riscv-tools/riscv-isa-sim](https://github.com/riscv-software-src/riscv-isa-sim) from `2890ea7` to `6f28e4b`. - [Release notes](https://github.com/riscv-software-src/riscv-isa-sim/releases) - [Commits](riscv-software-src/riscv-isa-sim@2890ea7...6f28e4b) --- updated-dependencies: - dependency-name: toolchains/riscv-tools/riscv-isa-sim dependency-type: direct:production ... Signed-off-by: dependabot[bot] <support@github.com>
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Bumps toolchains/riscv-tools/riscv-isa-sim from
2890ea7to6f28e4b.Commits
6f28e4bMerge pull request #1768 from riscv-software-src/commit-log-ordered8b05d84Use ordered map for commit log91793edMerge pull request #1764 from ved-rivos/extsddba69cupdate readme with extensionsf70b035Merge pull request #1763 from NXP/add-missing-extensions92833d1Add implemented extensions to readme11fbcb5Merge pull request #1758 from riscv-software-src/csr-init-fixes1b53bf9Merge pull request #1760 from YenHaoChen/pr-mxre749bb0Let MXR not affect implicit memory access for VS-stage address translation1ecad57Only add CSRs if corresponding extensions are enabledDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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