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Update rocket-chip with modern diplomacy/prci packaging #1895

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Jun 25, 2024
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Update rocket-chip with modern diplomacy/prci packaging #1895

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2 changes: 1 addition & 1 deletion fpga/fpga-shells
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Submodule fpga-shells updated 10 files
+1 −0 src/main/scala/devices/microsemi/polarfire_ddr3/MicrosemiPolarFireDDR3.scala
+1 −0 src/main/scala/devices/microsemi/polarfire_ddr4/MicrosemiPolarFireDDR4.scala
+1 −0 src/main/scala/devices/microsemi/polarfire_pcie/PolarFireEvalKitPCIeX4.scala
+1 −0 src/main/scala/devices/xilinx/allinxaxku040mig/AlinxAxku040MIG.scala
+1 −0 src/main/scala/devices/xilinx/xdma/XDMA.scala
+1 −0 src/main/scala/devices/xilinx/xilinxarty100tmig/XilinxArty100TMIG.scala
+1 −0 src/main/scala/devices/xilinx/xilinxnexysvideomig/XilinxNexysVideoMIG.scala
+1 −0 src/main/scala/devices/xilinx/xilinxvc707mig/XilinxVC707MIG.scala
+1 −0 src/main/scala/devices/xilinx/xilinxvc707pciex1/XilinxVC707PCIeX1.scala
+1 −0 src/main/scala/devices/xilinx/xilinxvcu118mig/XilinxVCU118MIG.scala
3 changes: 2 additions & 1 deletion fpga/src/main/scala/vc707/Configs.scala
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Expand Up @@ -6,7 +6,8 @@ import org.chipsalliance.cde.config.{Config, Parameters}
import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet}
import freechips.rocketchip.diplomacy.{RegionType, AddressSet}
import freechips.rocketchip.resources.{DTSModel, DTSTimebase}
import freechips.rocketchip.tile.{XLen}

import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams}
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3 changes: 2 additions & 1 deletion fpga/src/main/scala/vcu118/Configs.scala
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Expand Up @@ -6,7 +6,8 @@ import org.chipsalliance.cde.config.{Config, Parameters}
import freechips.rocketchip.subsystem.{SystemBusKey, PeripheryBusKey, ControlBusKey, ExtMem}
import freechips.rocketchip.devices.debug.{DebugModuleKey, ExportDebug, JTAG}
import freechips.rocketchip.devices.tilelink.{DevNullParams, BootROMLocated}
import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet}
import freechips.rocketchip.diplomacy.{RegionType, AddressSet}
import freechips.rocketchip.resources.{DTSModel, DTSTimebase}
import freechips.rocketchip.tile.{XLen}

import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams}
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2 changes: 1 addition & 1 deletion generators/boom
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Submodule boom updated 6 files
+1 −1 src/main/scala/v3/common/config-mixins.scala
+1 −1 src/main/scala/v3/common/tile.scala
+2 −1 src/main/scala/v3/lsu/tracegen.scala
+1 −1 src/main/scala/v4/common/config-mixins.scala
+1 −1 src/main/scala/v4/common/tile.scala
+2 −1 src/main/scala/v4/lsu/tracegen.scala
2 changes: 1 addition & 1 deletion generators/chipyard/src/main/scala/SpikeTile.scala
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Expand Up @@ -14,7 +14,7 @@ import freechips.rocketchip.tilelink._
import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.prci.ClockSinkParameters
import freechips.rocketchip.prci._

case class SpikeCoreParams() extends CoreParams {
val useVM = true
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1 change: 0 additions & 1 deletion generators/chipyard/src/main/scala/config/MMIOAcceleratorConfigs.scala
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@@ -1,7 +1,6 @@
package chipyard

import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}

// ------------------------------
// Configs with MMIO accelerators
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1 change: 0 additions & 1 deletion generators/chipyard/src/main/scala/config/MemorySystemConfigs.scala
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@@ -1,7 +1,6 @@
package chipyard

import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}

// ------------------------------------------------------------
// Configs which demonstrate modifying the uncore memory system
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1 change: 0 additions & 1 deletion generators/chipyard/src/main/scala/config/NoCConfigs.scala
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@@ -1,7 +1,6 @@
package chipyard

import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
import freechips.rocketchip.subsystem.{SBUS, MBUS}

import constellation.channel._
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1 change: 0 additions & 1 deletion generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala
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@@ -1,7 +1,6 @@
package chipyard

import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
import freechips.rocketchip.subsystem.{MBUS}

// ---------------------------------------------------------
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1 change: 0 additions & 1 deletion generators/chipyard/src/main/scala/config/RoCCAcceleratorConfigs.scala
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@@ -1,7 +1,6 @@
package chipyard

import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}

// ------------------------------
// Configs with RoCC Accelerators
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2 changes: 1 addition & 1 deletion generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -1,7 +1,7 @@
package chipyard

import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
import freechips.rocketchip.prci.{AsynchronousCrossing}
import freechips.rocketchip.subsystem.{InCluster}

// --------------
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2 changes: 1 addition & 1 deletion generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala
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Expand Up @@ -7,7 +7,7 @@ import chisel3.util.{log2Up}
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.devices.tilelink.{BootROMLocated, PLICKey, CLINTKey}
import freechips.rocketchip.devices.debug.{Debug, ExportDebug, DebugModuleKey, DMI, JtagDTMKey, JtagDTMConfig}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
import freechips.rocketchip.prci.{AsynchronousCrossing}
import chipyard.stage.phases.TargetDirKey
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tile.{XLen}
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2 changes: 1 addition & 1 deletion generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
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Expand Up @@ -2,7 +2,7 @@ package chipyard.config

import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy.{DTSTimebase}
import freechips.rocketchip.resources.{DTSTimebase}
import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}

// Replaces the L2 with a broadcast manager for maintaining coherence
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2 changes: 1 addition & 1 deletion generators/chipyard/src/main/scala/example/TutorialTile.scala
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Expand Up @@ -14,7 +14,7 @@ import freechips.rocketchip.interrupts._
import freechips.rocketchip.util._
import freechips.rocketchip.tile._
import freechips.rocketchip.amba.axi4._
import freechips.rocketchip.prci.ClockSinkParameters
import freechips.rocketchip.prci._

// Example parameter class copied from CVA6, not included in documentation but for compile check only
// If you are here for documentation, DO NOT copy MyCoreParams and MyTileParams directly - always figure
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2 changes: 1 addition & 1 deletion generators/constellation
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Submodule constellation updated 2 files
+1 −1 src/main/scala/channel/Channel.scala
+1 −1 src/main/scala/channel/Parameters.scala
2 changes: 1 addition & 1 deletion generators/cva6
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Submodule cva6 updated 2 files
+1 −2 src/main/scala/cva6/CVA6Tile.scala
+1 −1 src/main/scala/cva6/ConfigMixins.scala
5 changes: 3 additions & 2 deletions generators/firechip/src/main/scala/TargetConfigs.scala
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Expand Up @@ -12,7 +12,8 @@ import freechips.rocketchip.rocket.DCacheParams
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink.{BootROMLocated, BootROMParams}
import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
import freechips.rocketchip.diplomacy.{LazyModule, AsynchronousCrossing}
import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.prci.{AsynchronousCrossing}
import testchipip.iceblk.{BlockDeviceKey, BlockDeviceConfig}
import testchipip.cosim.{TracePortKey, TracePortParams}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
Expand Down Expand Up @@ -383,4 +384,4 @@ class FireSimLargeBoomSV39CospikeConfig extends Config(
new WithDefaultMemModel ++
new WithFireSimConfigTweaks++
new chipyard.config.WithSV39 ++
new chipyard.LargeBoomV3Config)
new chipyard.LargeBoomV3Config)
2 changes: 1 addition & 1 deletion generators/ibex
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Submodule ibex updated 1 files
+1 −1 src/main/scala/IbexTile.scala
2 changes: 1 addition & 1 deletion generators/icenet
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Submodule icenet updated 2 files
+1 −0 src/main/resources/csrc/switch.cc
+1 −0 src/main/scala/NIC.scala
2 changes: 1 addition & 1 deletion generators/riscv-sodor
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Submodule riscv-sodor updated 1 files
+1 −1 src/main/scala/sodor/common/sodor_tile.scala
2 changes: 1 addition & 1 deletion generators/rocket-chip
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Submodule rocket-chip updated 80 files
+2 −1 src/main/scala/amba/ahb/Parameters.scala
+2 −1 src/main/scala/amba/ahb/SRAM.scala
+2 −2 src/main/scala/amba/apb/Parameters.scala
+2 −1 src/main/scala/amba/apb/SRAM.scala
+1 −1 src/main/scala/amba/apb/ToTL.scala
+2 −1 src/main/scala/amba/axi4/AsyncCrossing.scala
+2 −1 src/main/scala/amba/axi4/Credited.scala
+1 −2 src/main/scala/amba/axi4/CrossingHelper.scala
+2 −1 src/main/scala/amba/axi4/Parameters.scala
+2 −1 src/main/scala/amba/axi4/RegisterRouter.scala
+2 −1 src/main/scala/amba/axi4/SRAM.scala
+1 −2 src/main/scala/amba/axi4/package.scala
+2 −1 src/main/scala/amba/axis/Parameters.scala
+2 −1 src/main/scala/devices/debug/Debug.scala
+2 −1 src/main/scala/devices/tilelink/BootROM.scala
+2 −1 src/main/scala/devices/tilelink/BusBlocker.scala
+2 −1 src/main/scala/devices/tilelink/CLINT.scala
+2 −1 src/main/scala/devices/tilelink/ClockBlocker.scala
+1 −0 src/main/scala/devices/tilelink/Deadlock.scala
+3 −1 src/main/scala/devices/tilelink/DevNull.scala
+1 −1 src/main/scala/devices/tilelink/Error.scala
+2 −1 src/main/scala/devices/tilelink/MaskROM.scala
+2 −1 src/main/scala/devices/tilelink/PhysicalFilter.scala
+2 −1 src/main/scala/devices/tilelink/Plic.scala
+2 −1 src/main/scala/devices/tilelink/TestRAM.scala
+2 −1 src/main/scala/devices/tilelink/Zero.scala
+0 −18 src/main/scala/diplomacy/AddressRange.scala
+62 −28 src/main/scala/diplomacy/package.scala
+2 −1 src/main/scala/groundtest/Tile.scala
+1 −2 src/main/scala/groundtest/TraceGen.scala
+1 −2 src/main/scala/interrupts/CrossingHelper.scala
+1 −1 src/main/scala/interrupts/Parameters.scala
+1 −1 src/main/scala/interrupts/RegisterRouter.scala
+1 −2 src/main/scala/interrupts/package.scala
+3 −3 src/main/scala/prci/ClockCrossingType.scala
+0 −2 src/main/scala/prci/ClockDomain.scala
+1 −1 src/main/scala/prci/ClockGroup.scala
+1 −1 src/main/scala/prci/ClockNodes.scala
+0 −2 src/main/scala/prci/IOHelper.scala
+0 −2 src/main/scala/prci/ResetCrossingType.scala
+3 −2 src/main/scala/prci/package.scala
+4 −1 src/main/scala/regmapper/RegisterRouter.scala
+21 −0 src/main/scala/resources/AddressMapEntry.scala
+2 −1 src/main/scala/resources/DeviceTree.scala
+1 −1 src/main/scala/resources/FixedClockResource.scala
+2 −1 src/main/scala/resources/JSON.scala
+7 −5 src/main/scala/resources/Resources.scala
+2 −1 src/main/scala/resources/SRAM.scala
+29 −0 src/main/scala/resources/package.scala
+2 −1 src/main/scala/rocket/DCache.scala
+2 −1 src/main/scala/rocket/ICache.scala
+2 −1 src/main/scala/rocket/ScratchpadSlavePort.scala
+3 −3 src/main/scala/subsystem/BaseSubsystem.scala
+1 −1 src/main/scala/subsystem/BusTopology.scala
+2 −2 src/main/scala/subsystem/Cluster.scala
+5 −2 src/main/scala/subsystem/Configs.scala
+1 −1 src/main/scala/subsystem/CrossingWrapper.scala
+1 −2 src/main/scala/subsystem/HasHierarchicalElements.scala
+2 −2 src/main/scala/subsystem/HasTiles.scala
+2 −2 src/main/scala/subsystem/HierarchicalElement.scala
+2 −2 src/main/scala/subsystem/HierarchicalElementPRCIDomain.scala
+2 −2 src/main/scala/subsystem/InterruptBus.scala
+4 −1 src/main/scala/subsystem/Ports.scala
+1 −1 src/main/scala/subsystem/RTC.scala
+1 −2 src/main/scala/subsystem/RocketSubsystem.scala
+3 −5 src/main/scala/tile/BaseTile.scala
+2 −1 src/main/scala/tile/BusErrorUnit.scala
+11 −5 src/main/scala/tile/FPU.scala
+2 −3 src/main/scala/tile/Interrupts.scala
+5 −3 src/main/scala/tile/RocketTile.scala
+2 −1 src/main/scala/tilelink/AsyncCrossing.scala
+2 −1 src/main/scala/tilelink/Broadcast.scala
+2 −2 src/main/scala/tilelink/BusWrapper.scala
+2 −1 src/main/scala/tilelink/Credited.scala
+3 −4 src/main/scala/tilelink/CrossingHelper.scala
+2 −1 src/main/scala/tilelink/Parameters.scala
+3 −1 src/main/scala/tilelink/RegisterRouter.scala
+2 −1 src/main/scala/tilelink/SRAM.scala
+1 −2 src/main/scala/tilelink/package.scala
+2 −1 src/main/scala/util/Annotations.scala
2 changes: 1 addition & 1 deletion generators/shuttle
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Submodule shuttle updated 2 files
+1 −1 src/main/scala/common/Configs.scala
+1 −1 src/main/scala/common/Tile.scala
2 changes: 1 addition & 1 deletion generators/testchipip
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Submodule testchipip updated 6 files
+3 −0 src/main/resources/testchipip/csrc/cospike.cc
+9 −0 src/main/resources/testchipip/csrc/cospike_impl.cc
+2 −0 src/main/resources/testchipip/csrc/cospike_impl.h
+8 −3 src/main/resources/testchipip/vsrc/cospike.v
+5 −1 src/main/scala/cosim/Cospike.scala
+1 −0 src/main/scala/iceblk/BlockDevice.scala
2 changes: 1 addition & 1 deletion tools/rocket-dsp-utils
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Submodule rocket-dsp-utils updated 2 files
+1 −0 src/main/scala/freechips/rocketchip/amba/axi4stream/CrossingHelper.scala
+1 −1 src/main/scala/freechips/rocketchip/amba/axi4stream/package.scala
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