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[WIP] Bare Metal VCU118 Capability #1892

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@BMorgan1296 BMorgan1296 commented May 31, 2024

Added new configs and harness binders for the VCU118 to use the UART TSI connection in the same way as the Arty

Issues: The non-TSI UART pins map to the same as the TSI pins, so I moved them to unused pins on the PMOD connectors, but this required modification of fpga-shells. Also, the LEDs do not work for the TSI connection yet.

Type of change:

  • Bug fix
  • New feature
  • Other enhancement

Impact:

  • RTL change
  • Software change (RISC-V software)
  • Build system change
  • Other

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…TSI connection in the same way as the Arty. Issues: The non-TSI UART pins map to the same as the TSI pins, so I moved them to unused pins on the PMOD connectors, but this required modification of fpga-shells. Also, the LEDs do not work for the TSI connection yet.
@BMorgan1296 BMorgan1296 changed the title Added new configs and harness binders for the VCU118 to use the UART TSI connection in the same way as the Arty [WIP] Bare Metal VCU118 Capability. May 31, 2024
@BMorgan1296 BMorgan1296 changed the title [WIP] Bare Metal VCU118 Capability. [WIP] Bare Metal VCU118 Capability May 31, 2024
@jerryz123
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The non-TSI UART pins map to the same as the TSI pins,

Right, you'd need a separate PMOD UART for the target UART

Also, the LEDs do not work for the TSI connection yet.

The LEDs were a debug feature when I was setting it up on the Arty. Not require for VCU118, but still very useful.

@BMorgan1296
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BMorgan1296 commented May 31, 2024

Right, you'd need a separate PMOD UART for the target UART

So would we want another PR for fpga-shells which implements a different PMOD UART which uses say the male connectors on the vcu118? There is no other spare female PMOD connector.

This will definitely need to be changed as the normal Linux test harness will need the UART over the USB, whereas with the bare-metal approach it can be put on PMOD like the Arty. Is there perhaps a way to override the pins specified in fpga-shell for this?

The LEDs were a debug feature when I was setting it up on the Arty. Not require for VCU118, but still very useful.

I will see if I can add them...

Anything else that needs to be done from what you can see?

@@ -63,6 +69,37 @@ class WithVCU118Tweaks extends Config(
new freechips.rocketchip.subsystem.WithNMemoryChannels(1)
)

class WithVCU118TweaksBareMetal extends Config(
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Can we drop the "BareMetal" naming, and name it UARTTSIVCU118 in all places. The "baremetal" terminology I feel does not accurately describe what the additional capability of these configs is.

harnessIO <> port.io.uart
val packagePinsWithPackageIOs = Seq(
("AW25" , IOPin(harnessIO.rxd)),
("BB21", IOPin(harnessIO.txd)))
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Your comment indicates that this overlaps with the UART device, which uses the UARTOverlay-generated pins in the VCU118TestHarness, but this generates its own pins. Do these overlap with the UARTOverlay pins?

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2 participants