Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Update deprecated APIs to prepare for Chisel 5 #1723

Merged
merged 1 commit into from
Jan 4, 2024
Merged

Update deprecated APIs to prepare for Chisel 5 #1723

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion generators/chipyard/src/main/scala/SpikeTile.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ package chipyard

import chisel3._
import chisel3.util._
import chisel3.experimental.{IntParam, StringParam, IO}
import chisel3.experimental.{IntParam, StringParam}

import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
Expand Down
2 changes: 1 addition & 1 deletion generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ package chipyard.clocking

import chisel3._
import chisel3.util._
import chisel3.experimental.{Analog, IO}
import chisel3.experimental.Analog

import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
Expand Down
2 changes: 1 addition & 1 deletion generators/chipyard/src/main/scala/clocking/TileClockGater.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ package chipyard.clocking

import chisel3._
import chisel3.util._
import chisel3.experimental.{Analog, IO}
import chisel3.experimental.Analog

import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
Expand Down
2 changes: 1 addition & 1 deletion generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@ package chipyard.clocking

import chisel3._
import chisel3.util._
import chisel3.experimental.{Analog, IO}
import chisel3.experimental.Analog

import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
Expand Down
3 changes: 2 additions & 1 deletion generators/chipyard/src/main/scala/iobinders/IOBinders.scala
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,7 +1,8 @@
package chipyard.iobinders

import chisel3._
import chisel3.experimental.{Analog, IO, DataMirror}
import chisel3.reflect.DataMirror
import chisel3.experimental.Analog

import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
Expand Down