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Rename timeout_cycles to TIMEOUT_CYCLES to match convention #1706

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Jan 11, 2024
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16 changes: 10 additions & 6 deletions variables.mk
Original file line number Diff line number Diff line change
Expand Up @@ -29,8 +29,7 @@ HELP_SIMULATION_VARIABLES = \
" LOADMEM = riscv elf binary that should be loaded directly into simulated DRAM. LOADMEM=1 will load the BINARY elf" \
" LOADARCH = path to a architectural checkpoint directory that should end in .loadarch/, for restoring from a checkpoint" \
" VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" \
" timeout_cycles = number of clock cycles before simulator times out, defaults to 10000000" \
" bmark_timeout_cycles = number of clock cycles before benchmark simulator times out, defaults to 100000000"
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" TIMEOUT_CYCLES = number of clock cycles before simulator times out, defaults to 10000000"

# include default simulation rules
HELP_COMMANDS = \
Expand Down Expand Up @@ -275,7 +274,7 @@ PERMISSIVE_ON=+permissive
PERMISSIVE_OFF=+permissive-off
BINARY ?=
BINARIES ?=
override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles)
override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(TIMEOUT_CYCLES)
VERBOSE_FLAGS ?= +verbose
# get_out_name is a function, 1st argument is the binary
get_out_name = $(subst $() $(),_,$(notdir $(basename $(1))))
Expand All @@ -301,7 +300,12 @@ build_dir =$(gen_dir)/$(long_name)
GEN_COLLATERAL_DIR ?=$(build_dir)/gen-collateral

#########################################################################################
# assembly/benchmark variables
# simulation variables
#########################################################################################
timeout_cycles = 10000000
bmark_timeout_cycles = 100000000
TIMEOUT_CYCLES = 10000000

# legacy timeout_cycles handling
timeout_cycles ?=
ifneq ($(timeout_cycles),)
TIMEOUT_CYCLES=$(timeout_cycles)
endif
2 changes: 1 addition & 1 deletion vlsi/power.mk
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ endif
endif
echo " start_times: ['0ns']" >> $@
echo " end_times: [" >> $@
echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
echo " '`bc <<< $(TIMEOUT_CYCLES)*$(CLOCK_PERIOD)`ns'" >> $@
echo " ]" >> $@

$(POWER_RTL_CONF): $(VLSI_RTL)
Expand Down
2 changes: 1 addition & 1 deletion vlsi/sim.mk
Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@ endif
echo " execution_flags_meta: 'append'" >> $@
echo " saif.mode: 'time'" >> $@
echo " saif.start_time: '0ns'" >> $@
echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
echo " saif.end_time: '`bc <<< $(TIMEOUT_CYCLES)*$(CLOCK_PERIOD)`ns'" >> $@
ifndef USE_VPD
echo " options:" >> $@
echo ' - "-kdb"' >> $@
Expand Down
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