Add HasHarnessInstantiators into MultiHarnessBinder

generators/chipyard/src/main/scala/harness/MultiHarnessBinders.scala

@@ -24,18 +24,18 @@ object ApplyMultiHarnessBinders {
     Seq.tabulate(chips.size, chips.size) { case (i, j) => if (i != j) {
       (chips(i), chips(j)) match {
         case (l0: HasChipyardPorts, l1: HasChipyardPorts) => p(MultiHarnessBinders(i, j)).foreach { f =>
-          f(l0.ports, l1.ports)
+          f(th, l0.ports, l1.ports)
         }
       }
     }}
   }
 }
 
-class MultiHarnessBinder[T <: Port[_]](
+class MultiHarnessBinder[T <: Port[_], S <: HasHarnessInstantiators](
   chip0: Int, chip1: Int,
   chip0portFn: T => Boolean, chip1portFn: T => Boolean,
-  connectFn: (T, T) => Unit
-)(implicit tag: ClassTag[T]) extends Config((site, here, up) => {
+  connectFn: (S, T, T) => Unit
+)(implicit tag0: ClassTag[T], tag1: ClassTag[S]) extends Config((site, here, up) => {
     // Override any HarnessBinders for chip0/chip1
     case MultiChipParameters(`chip0`) => new Config(
       new HarnessBinder({case (th, port: T) if chip0portFn(port) => }) ++ up(MultiChipParameters(chip0))
@@ -45,21 +45,21 @@ class MultiHarnessBinder[T <: Port[_]](
     )
     // Set the multiharnessbinder key
     case MultiHarnessBinders(`chip0`, `chip1`) => up(MultiHarnessBinders(chip0, chip1)) :+ {
-      ((chip0Ports: Seq[Port[_]], chip1Ports: Seq[Port[_]]) => {
+      ((th: S, chip0Ports: Seq[Port[_]], chip1Ports: Seq[Port[_]]) => {
         val chip0Port: Seq[T] = chip0Ports.collect { case (p: T) if chip0portFn(p) => p }
         val chip1Port: Seq[T] = chip1Ports.collect { case (p: T) if chip1portFn(p) => p }
         require(chip0Port.size == 1 && chip1Port.size == 1)
-        connectFn(chip0Port(0), chip1Port(0))
+        connectFn(th, chip0Port(0), chip1Port(0))
       })
     }
   })
 
 
-class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1portId: Int = 0) extends MultiHarnessBinder[SerialTLPort](
+class WithMultiChipSerialTL(chip0: Int, chip1: Int, chip0portId: Int = 0, chip1portId: Int = 0) extends MultiHarnessBinder(
   chip0, chip1,
   (p0: SerialTLPort) => p0.portId == chip0portId,
   (p1: SerialTLPort) => p1.portId == chip1portId,
-  (p0: SerialTLPort, p1: SerialTLPort) => {
+  (th: HasHarnessInstantiators, p0: SerialTLPort, p1: SerialTLPort) => {
     (DataMirror.directionOf(p0.io.clock), DataMirror.directionOf(p1.io.clock)) match {
       case (Direction.Input, Direction.Output) => p0.io.clock := p1.io.clock
       case (Direction.Output, Direction.Input) => p1.io.clock := p0.io.clock

generators/chipyard/src/main/scala/harness/package.scala

@@ -7,5 +7,5 @@ package object harness
 {
   import chipyard.iobinders.Port
   type HarnessBinderFunction = PartialFunction[(HasHarnessInstantiators, Port[_]), Unit]
-  type MultiHarnessBinderFunction = (Seq[Port[_]], Seq[Port[_]]) => Unit
+  type MultiHarnessBinderFunction = (HasHarnessInstantiator, Seq[Port[_]], Seq[Port[_]]) => Unit
 }