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Move boom's tracegen interface to boom submodule #1331

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merged 1 commit into from
Feb 11, 2023
Merged

Move boom's tracegen interface to boom submodule #1331

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2 changes: 1 addition & 1 deletion generators/boom
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Submodule boom updated 2 files
+2 −2 src/main/scala/exu/core.scala
+256 −0 src/main/scala/lsu/tracegen.scala
1 change: 1 addition & 0 deletions generators/tracegen/src/main/scala/Configs.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,7 @@ import freechips.rocketchip.subsystem._
import freechips.rocketchip.system.BaseConfig
import freechips.rocketchip.rocket.DCacheParams
import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
import boom.lsu._
import scala.math.{max, min}

class WithTraceGen(
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1 change: 1 addition & 0 deletions generators/tracegen/src/main/scala/System.scala
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Expand Up @@ -6,6 +6,7 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple}
import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile}
import freechips.rocketchip.subsystem._
import boom.lsu.BoomTraceGenTile

class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
with HasTiles
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256 changes: 0 additions & 256 deletions generators/tracegen/src/main/scala/Tile.scala
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