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changelog: fixed TinyRocketArtyConfig FPGA reset signal polarity (Please Backport) #1257

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merged 1 commit into from
Dec 8, 2022

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T-K-233
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@T-K-233 T-K-233 commented Oct 16, 2022

changelog: fixed Arty FPGA reset signal polarity

Related PRs / Issues:

Fix of issue #1256

Type of change:

  • Bug fix
  • New feature
  • Other enhancement

Impact:

  • RTL change
  • Software change (RISC-V software)
  • Build system change
  • Other

Contributor Checklist:

  • Did you set main as the base branch?
  • Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
  • Did you state the type-of-change/impact?
  • Did you delete any extraneous prints/debugging code?
  • Did you mark the PR with a changelog: label?
  • (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
  • (If applicable) Did you add documentation for the feature?
  • (If applicable) Did you add a test demonstrating the PR?
  • (If applicable) Did you mark the PR as Please Backport?

@T-K-233 T-K-233 changed the title changelog: fixed Arty FPGA reset signal polarity (Please Backport) changelog: fixed TinyRocketArtyConfig FPGA reset signal polarity (Please Backport) Oct 16, 2022
@jerryz123
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@abejgonzalez should we backport this?

@abejgonzalez
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Probably. Unfortunately, we have no automation for this right now so this has to be done by hand.

@jerryz123 jerryz123 self-requested a review December 8, 2022 03:34
@jerryz123 jerryz123 merged commit 1b7457d into ucb-bar:main Dec 8, 2022
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3 participants