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Clean multiclock support #662

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jerryz123 opened this issue Aug 26, 2020 · 5 comments
Closed
7 tasks done

Clean multiclock support #662

jerryz123 opened this issue Aug 26, 2020 · 5 comments

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@jerryz123
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jerryz123 commented Aug 26, 2020

This issue tracks work towards clean support of multiclock designs. The vision is to use rocketchip's new diplomatic clock graph as an API to determine how to generate and connect clocks for a multiclock design.

Impact: rtl

@colinschmidt
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I think we should make SimSerial behave like it does on most test-chips where it provides it's clock off chip to be caught by the testharness and used to synchronize the "serial" data.
This doesn't change the fact that SimDRAM probably needs this feature (since it isn't meant to be used in the same way as SimSerial).

@jerryz123
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I agree we should make Serial more "correct". If that leaves SimDRAM as the only widget for which punching out a clock is necessary, then I think we should just special-case it.
However, if other use cases (like SimNetwork for the NIC) also want to live in TestHarness, and need to be clocked by a chip-internal clock, it may be worth the effort to develop a more generic solution.

@alonamid
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Don't forget multi-clock example + documentation

@jerryz123
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When this is complete, all default examples will be multi-clock

@jerryz123
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Released in 1.4.0

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