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Default enable XS bit in riscv-pk #571

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alonamid opened this issue May 26, 2020 · 1 comment
Closed

Default enable XS bit in riscv-pk #571

alonamid opened this issue May 26, 2020 · 1 comment

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@alonamid
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Impact: software

Description

The XS bit in mstatus is not enabled by default in riscv-pk. This requires manual code patching in order to use pk with RoCC accelerators.
We did not arrive at a decision for pk pre-release (since the toolchains currently do not have a riscv-pk fork). This should be addressed in the next toolchains bump.

What is a motivating example for changing the behavior?
Running pk programs using Hwacha/Gemmini
@alonamid
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alonamid commented Jul 7, 2020

Resolved (in rocketchip) in #605

@alonamid alonamid closed this as completed Jul 7, 2020
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@alonamid