How to Add a prefix at every module name when generating system verilog?

[csgxiong]

Background Work

• Yes, I searched the mailing list
• Yes, I searched the documentation

Feature Description

How to Add a prefix at every module name when generating system verilog?

Motivating Example

I want to Add a prefix at every module name when generating system verilog,
such as: DigitalTop >> Chipyard_DigitalTop
TLDebugModule >> Chipyard_TLDebugModule
So Does anyone have any ideas on this issue?

Thanks.

[jerryz123]

I don't think there's anything readily set up. Perhaps one way is to look into the NestedPrefixModuleAnnotation