Fix Reset bug

ucb-bar · Aug 5, 2020 · f69b293 · f69b293
1 parent 9e44313
commit f69b293
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala
@@ -120,7 +120,7 @@ class WithFireSimRationalTileDomain(multiplier: Int, divisor: Int) extends Confi
             data.reset := ResetCatchAndSync(tile_clock, reset.asBool)
           } else {
             data.clock := uncore_clock
-            data.clock := reset
+            data.reset := reset
           }
         }
       }}

diff --git a/generators/tracegen/src/main/scala/Tile.scala b/generators/tracegen/src/main/scala/Tile.scala
@@ -210,7 +210,7 @@ class BoomTraceGenTile private(
 
   val boom_params = p.alterMap(Map(TileKey -> BoomTileParams(
     dcache=params.dcache,
-    core=BoomCoreParams(nPMPs=0, numLdqEntries=32, numStqEntries=32, useVM=false))))
+    core=BoomCoreParams(nPMPs=0, numLdqEntries=16, numStqEntries=16, useVM=false))))
   val dcache = LazyModule(new BoomNonBlockingDCache(staticIdForMetadataUseOnly)(boom_params))