Initial Makefile changes

sims/verilator/Makefile

@@ -28,8 +28,6 @@ sim_prefix = simulator
 sim = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)
 sim_debug = $(sim_dir)/$(sim_prefix)-$(MODEL_PACKAGE)-$(CONFIG)-debug
 
-WAVEFORM_FLAG=-v$(sim_out_name).vcd
-
 include $(base_dir)/sims/common-sim-flags.mk
 
 # If verilator seed unspecified, verilator uses srand as random seed
@@ -47,23 +45,7 @@ debug: $(sim_debug)
 # simulaton requirements
 #########################################################################################
 SIM_FILE_REQS += \
-	$(CHIPYARD_RSRCS_DIR)/csrc/emulator.cc \
-	$(ROCKETCHIP_RSRCS_DIR)/csrc/verilator.h \
-
-# the following files are needed for emulator.cc to compile (even if they aren't part of the RTL build)
-SIM_FILE_REQS += \
-	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimSerial.cc \
-	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.cc \
-	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/testchip_tsi.h \
-	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/SimDRAM.cc \
-	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.h \
-	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm.cc \
-	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.h \
-	$(TESTCHIP_RSRCS_DIR)/testchipip/csrc/mm_dramsim2.cc \
-	$(ROCKETCHIP_RSRCS_DIR)/csrc/SimDTM.cc \
-	$(ROCKETCHIP_RSRCS_DIR)/csrc/SimJTAG.cc \
-	$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.h \
-	$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc
+	$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v
 
 # copy files and add -FI for *.h files in *.f
 $(sim_files): $(SIM_FILE_REQS) $(ALL_MODS_FILELIST) | $(GEN_COLLATERAL_DIR)
@@ -92,7 +74,7 @@ HELP_COMPILATION_VARIABLES += \
 #########################################################################################
 # verilator/cxx binary and flags
 #########################################################################################
-VERILATOR := verilator --cc --exe --timing
+VERILATOR := verilator --main --timing --cc --exe
 
 #----------------------------------------------------------------------------------------
 # user configs
@@ -107,10 +89,11 @@ RUNTIME_PROFILING_VFLAGS := $(if $(filter $(VERILATOR_PROFILE),all),\
 VERILATOR_THREADS ?= 1
 RUNTIME_THREADS := --threads $(VERILATOR_THREADS) --threads-dpi all
 
-VERILATOR_FST_MODE ?= 0
+VERILATOR_FST_MODE ?= 1
 TRACING_OPTS := $(if $(filter $(VERILATOR_FST_MODE),0),\
 	                  --trace,--trace-fst --trace-threads 1)
-TRACING_CFLAGS := $(if $(filter $(VERILATOR_FST_MODE),0),,-DCY_FST_TRACE)
+WAVEFORM_FLAG := +vcdfile=$(sim_out_name).$(if $(filter $(VERILATOR_FST_MODE),0),\
+	                  vcd,fst)
 
 #----------------------------------------------------------------------------------------
 # verilation configuration/optimization
@@ -153,9 +136,16 @@ TIMESCALE_OPTS := $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1
 # see: https://github.com/ucb-bar/riscv-mini/issues/31
 MAX_WIDTH_OPTS = $(shell verilator --version | perl -lne 'if (/(\d.\d+)/ && $$1 > 4.016) { print "--max-num-width 1048576"; }')
 
+# TODO DEDUP
+CLOCK_PERIOD ?= 1.0
+RESET_DELAY ?= 777.7
+
 PREPROC_DEFINES := \
-	+define+PRINTF_COND=\$$c\(\"verbose\",\"\&\&\"\,\"done_reset\"\) \
-	+define+STOP_COND=\$$c\(\"done_reset\"\)
+	+define+CLOCK_PERIOD=$(CLOCK_PERIOD) \
+	+define+RESET_DELAY=$(RESET_DELAY) \
+	+define+PRINTF_COND=$(TB).printf_cond \
+	+define+STOP_COND=!$(TB).reset \
+	+define+MODEL=$(MODEL)
 
 VERILATOR_NONCC_OPTS = \
 	$(RUNTIME_PROFILING_VFLAGS) \
@@ -166,7 +156,7 @@ VERILATOR_NONCC_OPTS = \
 	$(TIMESCALE_OPTS) \
 	$(MAX_WIDTH_OPTS) \
 	$(PREPROC_DEFINES) \
-	--top-module $(VLOG_MODEL) \
+	--top-module $(TB) \
 	--vpi \
 	-f $(sim_common_files)
 
@@ -176,12 +166,9 @@ VERILATOR_NONCC_OPTS = \
 VERILATOR_CXXFLAGS = \
 	$(SIM_CXXFLAGS) \
 	$(RUNTIME_PROFILING_CFLAGS) \
-	$(TRACING_CFLAGS) \
 	-D__STDC_FORMAT_MACROS \
-	-DTEST_HARNESS=V$(VLOG_MODEL) \
 	-DVERILATOR \
-	-include $(build_dir)/$(long_name).plusArgs \
-	-include $(GEN_COLLATERAL_DIR)/verilator.h
+	-include $(build_dir)/$(long_name).plusArgs
 
 VERILATOR_LDFLAGS = $(SIM_LDFLAGS)
 
@@ -200,11 +187,11 @@ VERILATOR_OPTS = $(VERILATOR_CC_OPTS) $(VERILATOR_NONCC_OPTS)
 model_dir = $(build_dir)/$(long_name)
 model_dir_debug = $(build_dir)/$(long_name).debug
 
-model_header = $(model_dir)/V$(VLOG_MODEL).h
-model_header_debug = $(model_dir_debug)/V$(VLOG_MODEL).h
+model_header = $(model_dir)/V$(TB).h
+model_header_debug = $(model_dir_debug)/V$(TB).h
 
-model_mk = $(model_dir)/V$(VLOG_MODEL).mk
-model_mk_debug = $(model_dir_debug)/V$(VLOG_MODEL).mk
+model_mk = $(model_dir)/V$(TB).mk
+model_mk_debug = $(model_dir_debug)/V$(TB).mk
 
 #########################################################################################
 # build makefile fragment that builds the verilator sim rules
@@ -218,17 +205,17 @@ $(model_mk): $(sim_common_files) $(EXTRA_SIM_REQS)
 $(model_mk_debug): $(sim_common_files) $(EXTRA_SIM_REQS)
 	rm -rf $(model_dir_debug)
 	mkdir -p $(model_dir_debug)
-	$(VERILATOR) $(VERILATOR_OPTS) $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
+	$(VERILATOR) $(VERILATOR_OPTS) +define+DEBUG $(EXTRA_SIM_SOURCES) -o $(sim_debug) $(TRACING_OPTS) -Mdir $(model_dir_debug) -CFLAGS "-include $(model_header_debug)"
 	touch $@
 
 #########################################################################################
 # invoke make to make verilator sim rules
 #########################################################################################
 $(sim): $(model_mk) $(dramsim_lib)
-	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(VLOG_MODEL).mk
+	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir) -f V$(TB).mk
 
 $(sim_debug): $(model_mk_debug) $(dramsim_lib)
-	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(VLOG_MODEL).mk
+	$(MAKE) VM_PARALLEL_BUILDS=1 -C $(model_dir_debug) -f V$(TB).mk
 
 #########################################################################################
 # create a verilator vpd rule