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Merge pull request #1854 from ucb-bar/chisel6-attempt2
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Support Chisel6 for RTL-sim/VLSI/FPGA flows
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jerryz123 authored May 13, 2024
2 parents 5870c6e + 3cda03a commit e2f4ea6
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14 changes: 2 additions & 12 deletions .github/scripts/check-commit.sh
Original file line number Diff line number Diff line change
Expand Up @@ -45,21 +45,11 @@ search () {
done
}

submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy")
submodules=("cva6" "boom" "ibex" "gemmini" "icenet" "nvdla" "rocket-chip" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils" "diplomacy")
dir="generators"
branches=("master" "main" "dev")
search

submodules=("esp-tools-feedstock")
dir="toolchains/esp-tools"
branches=("main")
search

submodules=("riscv-isa-sim" "riscv-pk" "riscv-tests")
dir="toolchains/esp-tools"
branches=("master")
search

submodules=("riscv-tools-feedstock")
dir="toolchains/riscv-tools"
branches=("main")
Expand Down Expand Up @@ -92,7 +82,7 @@ dir="software"
branches=("master" "dev")
search

submodules=("DRAMSim2" "axe" "dsptools" "rocket-dsp-utils" "torture" "fixedpoint" "cde")
submodules=("DRAMSim2" "axe" "dsptools" "dsptools-chisel3" "rocket-dsp-utils" "torture" "fixedpoint" "fixedpoint-chisel3" "cde" "midas-targetutils")
dir="tools"
branches=("master" "dev" "main")
search
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4 changes: 1 addition & 3 deletions .github/scripts/defaults.sh
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ REMOTE_COURSIER_CACHE=$REMOTE_WORK_DIR/.coursier-cache
declare -A grouping
grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boomv3 chipyard-boomv4 chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad chipyard-spike chipyard-clone chipyard-prefetchers chipyard-shuttle"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboomv3 chipyard-dmiboomv4 chipyard-spiflashwrite chipyard-mmios chipyard-nocores chipyard-manyperipherals chipyard-chiplike chipyard-tethered chipyard-symmetric chipyard-llcchiplet"
grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
grouping["group-accels"]="chipyard-mempress chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
grouping["group-constellation"]="chipyard-constellation"
grouping["group-tracegen"]="tracegen tracegen-boomv3 tracegen-boomv4"
grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters"
Expand All @@ -40,7 +40,6 @@ grouping["group-fpga"]="arty35t arty100t nexysvideo vc707 vcu118"
declare -A mapping
mapping["chipyard-rocket"]=" CONFIG=QuadChannelRocketConfig"
mapping["chipyard-dmirocket"]=" CONFIG=dmiRocketConfig"
mapping["chipyard-sha3"]=" CONFIG=Sha3RocketConfig"
mapping["chipyard-mempress"]=" CONFIG=MempressRocketConfig"
mapping["chipyard-prefetchers"]=" CONFIG=PrefetchingRocketConfig"
mapping["chipyard-digitaltop"]=" TOP=DigitalTop"
Expand All @@ -52,7 +51,6 @@ mapping["chipyard-dmiboomv3"]=" CONFIG=dmiMediumBoomV3CosimConfig"
mapping["chipyard-boomv4"]=" CONFIG=MediumBoomV4CosimConfig"
mapping["chipyard-dmiboomv4"]=" CONFIG=dmiMediumBoomV4CosimConfig"
mapping["chipyard-spike"]=" CONFIG=SpikeConfig EXTRA_SIM_FLAGS='+spike-ipc=10'"
mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
mapping["chipyard-ibex"]=" CONFIG=IbexConfig"
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7 changes: 0 additions & 7 deletions .github/scripts/run-tests.sh
Original file line number Diff line number Diff line change
Expand Up @@ -77,9 +77,6 @@ case $1 in
rocketchip)
run_bmark
;;
chipyard-hwacha)
make run-rv64uv-p-asm-tests -j$CI_MAKE_NPROC -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ $MAPPING_FLAGS
;;
chipyard-gemmini)
GEMMINI_SOFTWARE_DIR=$LOCAL_SIM_DIR/../../generators/gemmini/software/gemmini-rocc-tests
rm -rf $GEMMINI_SOFTWARE_DIR/riscv-tests
Expand All @@ -88,10 +85,6 @@ case $1 in
run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/raw_hazard-baremetal
run_binary BINARY=$GEMMINI_SOFTWARE_DIR/build/bareMetalC/mvin_mvout-baremetal
;;
chipyard-sha3)
(cd $LOCAL_CHIPYARD_DIR/generators/sha3/software && ./build.sh)
run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/sha3/software/tests/bare/sha3-rocc.riscv
;;
chipyard-mempress)
(cd $LOCAL_CHIPYARD_DIR/generators/mempress/software/src && make)
run_binary BINARY=$LOCAL_CHIPYARD_DIR/generators/mempress/software/src/mempress-rocc.riscv
Expand Down
18 changes: 3 additions & 15 deletions .github/workflows/chipyard-full-flow.yml
Original file line number Diff line number Diff line change
Expand Up @@ -61,8 +61,8 @@ jobs:
- '**/.gitignore'
- '.github/ISSUE_TEMPLATE/**'
setup-repo:
name: setup-repo
full-flow:
name: full-flow
needs: [change-filters, cancel-prior-workflows]
if: needs.change-filters.outputs.needs-rtl == 'true'
runs-on: as4
Expand All @@ -84,25 +84,13 @@ jobs:
mkdir ${{ env.JAVA_TMP_DIR }}
export MAKEFLAGS="-j32"
./build-setup.sh -v
run-cfg-finder:
name: run-cfg-finder
needs: [setup-repo]
runs-on: as4
steps:
- name: Run config finder
run: |
cd ${{ env.REMOTE_WORK_DIR }}
eval "$(conda shell.bash hook)"
source env.sh
cd sims/verilator
make find-config-fragments
run-tutorial:
name: run-tutorial
needs: [setup-repo]
runs-on: as4
steps:
- name: Run smoke test
run: |
cd ${{ env.REMOTE_WORK_DIR }}
Expand Down Expand Up @@ -169,7 +157,7 @@ jobs:
cleanup:
name: cleanup
needs: [run-tutorial]
needs: [full-flow]
runs-on: as4
if: ${{ always() }}
steps:
Expand Down
48 changes: 0 additions & 48 deletions .github/workflows/chipyard-run-tests.yml
Original file line number Diff line number Diff line change
Expand Up @@ -119,29 +119,6 @@ jobs:
conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
.github/scripts/check-commit.sh
tutorial-setup-check:
name: tutorial-setup-check
needs: [setup-complete]
if: needs.change-filters.outputs.needs-rtl == 'true'
runs-on: as4
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Check that the tutorial-setup patches apply
run: |
conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools
scripts/tutorial-setup.sh
documentation-check:
name: documentation-check
needs: [setup-complete]
Expand Down Expand Up @@ -800,29 +777,6 @@ jobs:
group-key: "group-peripherals"
project-key: "chipyard-llcchiplet"

chipyard-sha3-run-tests:
name: chipyard-sha3-run-tests
needs: prepare-chipyard-accels
runs-on: as4
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-accels"
project-key: "chipyard-sha3"

chipyard-gemmini-run-tests:
name: chipyard-gemmini-run-tests
needs: prepare-chipyard-accels
Expand Down Expand Up @@ -1172,7 +1126,6 @@ jobs:
all_tests_passed:
name: "all tests passed"
needs: [commit-on-master-check,
tutorial-setup-check,
documentation-check,
chipyard-rocket-run-tests,
chipyard-hetero-run-tests,
Expand All @@ -1190,7 +1143,6 @@ jobs:
chipyard-tethered-run-tests,
chipyard-symmetric-run-tests,
chipyard-llcchiplet-run-tests,
chipyard-sha3-run-tests,
chipyard-gemmini-run-tests,
chipyard-manymmioaccels-run-tests, # chipyard-nvdla-run-tests,
chipyard-prefetchers-run-tests,
Expand Down
36 changes: 14 additions & 22 deletions .gitmodules
Original file line number Diff line number Diff line change
Expand Up @@ -28,9 +28,6 @@
[submodule "generators/hardfloat"]
path = generators/hardfloat
url = https://github.com/ucb-bar/berkeley-hardfloat.git
[submodule "generators/hwacha"]
path = generators/hwacha
url = https://github.com/ucb-bar/hwacha.git
[submodule "generators/ibex"]
path = generators/ibex
url = https://github.com/ucb-bar/ibex-wrapper.git
Expand Down Expand Up @@ -58,9 +55,6 @@
[submodule "generators/rocket-chip-inclusive-cache"]
path = generators/rocket-chip-inclusive-cache
url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
[submodule "generators/sha3"]
path = generators/sha3
url = https://github.com/ucb-bar/sha3.git
[submodule "generators/shuttle"]
path = generators/shuttle
url = https://github.com/ucb-bar/shuttle.git
Expand Down Expand Up @@ -88,18 +82,6 @@
[submodule "software/spec2017"]
path = software/spec2017
url = https://github.com/ucb-bar/spec2017-workload.git
[submodule "toolchains/esp-tools/esp-tools-feedstock"]
path = toolchains/esp-tools/esp-tools-feedstock
url = https://github.com/ucb-bar/esp-tools-feedstock.git
[submodule "toolchains/esp-tools/riscv-isa-sim"]
path = toolchains/esp-tools/riscv-isa-sim
url = https://github.com/ucb-bar/esp-isa-sim.git
[submodule "toolchains/esp-tools/riscv-pk"]
path = toolchains/esp-tools/riscv-pk
url = https://github.com/riscv-software-src/riscv-pk.git
[submodule "toolchains/esp-tools/riscv-tests"]
path = toolchains/esp-tools/riscv-tests
url = https://github.com/ucb-bar/esp-tests.git
[submodule "toolchains/libgloss"]
path = toolchains/libgloss
url = https://github.com/ucb-bar/libgloss-htif.git
Expand Down Expand Up @@ -133,11 +115,11 @@
[submodule "tools/circt"]
path = tools/circt
url = https://github.com/llvm/circt.git
[submodule "tools/dsptools"]
path = tools/dsptools
[submodule "tools/dsptools-fixedpoint"]
path = tools/dsptools-chisel3
url = https://github.com/ucb-bar/dsptools.git
[submodule "tools/fixedpoint"]
path = tools/fixedpoint
[submodule "tools/fixedpoint-chisel3"]
path = tools/fixedpoint-chisel3
url = https://github.com/ucb-bar/fixedpoint.git
[submodule "tools/install-circt"]
path = tools/install-circt
Expand All @@ -151,3 +133,13 @@
[submodule "vlsi/hammer-mentor-plugins"]
path = vlsi/hammer-mentor-plugins
url = https://github.com/ucb-bar/hammer-mentor-plugins.git
[submodule "tools/dsptools"]
path = tools/dsptools
url = https://github.com/ucb-bar/dsptools.git
[submodule "tools/fixedpoint"]
path = tools/fixedpoint
url = https://github.com/ucb-bar/fixedpoint.git
[submodule "tools/midas-targetutils"]
path = tools/midas-targetutils
url = https://github.com/firesim/midas-targetutils.git

4 changes: 1 addition & 3 deletions README.md
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ To get started using Chipyard, see the stable documentation on the Chipyard docu

Chipyard is an open source framework for agile development of Chisel-based systems-on-chip.
It will allow you to leverage the Chisel HDL, Rocket Chip SoC generator, and other [Berkeley][berkeley] projects to produce a [RISC-V][riscv] SoC with everything from MMIO-mapped peripherals to custom accelerators.
Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), accelerators ([Hwacha][hwacha], [Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
Chipyard contains processor cores ([Rocket][rocket-chip], [BOOM][boom], [CVA6 (Ariane)][cva6]), accelerators ([Gemmini][gemmini], [NVDLA][nvdla]), memory systems, and additional peripherals and tooling to help create a full featured SoC.
Chipyard supports multiple concurrent flows of agile hardware development, including software RTL simulation, FPGA-accelerated simulation ([FireSim][firesim]), automated VLSI flows ([Hammer][hammer]), and software workload generation for bare-metal and Linux-based systems ([FireMarshal][firemarshal]).
Chipyard is actively developed in the [Berkeley Architecture Research Group][ucb-bar] in the [Electrical Engineering and Computer Sciences Department][eecs] at the [University of California, Berkeley][berkeley].

Expand Down Expand Up @@ -65,7 +65,6 @@ These additional publications cover many of the internal components used in Chip
* **BOOM**: C. Celio, et al., *Hot Chips 30*. [PDF](https://old.hotchips.org/hc30/1conf/1.03_Berkeley_BROOM_HC30.Berkeley.Celio.v02.pdf).
* **SonicBOOM (BOOMv3)**: J. Zhao, et al., *CARRV'20*. [PDF](https://carrv.github.io/2020/papers/CARRV2020_paper_15_Zhao.pdf).
* **COBRA (BOOM Branch Prediction)**: J. Zhao, et al., *ISPASS'21*. [PDF](https://ieeexplore.ieee.org/document/9408173).
* **Hwacha**: Y. Lee, et al., *ESSCIRC'14*. [PDF](http://hwacha.org/papers/riscv-esscirc2014.pdf).
* **Gemmini**: H. Genc, et al., *DAC'21*. [PDF](https://arxiv.org/pdf/1911.09925).
* **Sims**
* **FireSim**: S. Karandikar, et al., *ISCA'18*. [PDF](https://sagark.org/assets/pubs/firesim-isca2018.pdf).
Expand All @@ -87,7 +86,6 @@ These additional publications cover many of the internal components used in Chip

This work is supported by the NSF CCRI ENS Chipyard Award #2016662.

[hwacha]:https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-262.pdf
[hammer]:https://github.com/ucb-bar/hammer
[firesim]:https://fires.im
[ucb-bar]: http://bar.eecs.berkeley.edu
Expand Down
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