Bump Rocketchip to June 2020 for Tile changes

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -4,20 +4,23 @@ import chisel3._
 import chisel3.util.{log2Up}
 
 import freechips.rocketchip.config.{Field, Parameters, Config}
-import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, CacheBlockBytes}
+import freechips.rocketchip.subsystem._
 import freechips.rocketchip.diplomacy.{LazyModule, ValName}
 import freechips.rocketchip.devices.tilelink.BootROMParams
 import freechips.rocketchip.devices.debug.{Debug}
-import freechips.rocketchip.tile.{XLen, BuildRoCC, TileKey, LazyRoCC, RocketTileParams, MaxHartIdBits}
+import freechips.rocketchip.groundtest.{GroundTestSubsystem}
+import freechips.rocketchip.tile._
 import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
 import freechips.rocketchip.util.{AsyncResetReg}
 
-import boom.common.{BoomTilesKey}
-import ariane.{ArianeTilesKey}
 import testchipip._
+import tracegen.{TraceGenSystem}
 
 import hwacha.{Hwacha}
 
+import boom.common.{BoomTileAttachParams}
+import ariane.{ArianeTileAttachParams}
+
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
 import sifive.blocks.devices.spi._
@@ -60,26 +63,17 @@ class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) =>
 })
 
 class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
-  case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
-    core = tile.core.copy(nL2TLBEntries = entries)
-  ))
-  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(
-    core = tile.core.copy(nL2TLBEntries = entries)
-  ))
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
+    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
+    case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
+    case other => other
+  }
 })
 
 class WithTracegenSystem extends Config((site, here, up) => {
-  case BuildSystem => (p: Parameters) => LazyModule(new tracegen.TraceGenSystem()(p))
-})
-
-class WithRenumberHarts(rocketFirst: Boolean = false) extends Config((site, here, up) => {
-  case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) =>
-    r.copy(hartId = i + (if(rocketFirst) 0 else up(BoomTilesKey, site).length))
-  }
-  case BoomTilesKey => up(BoomTilesKey, site).zipWithIndex map { case (b, i) =>
-    b.copy(hartId = i + (if(rocketFirst) up(RocketTilesKey, site).length else 0))
-  }
-  case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size)
+  case BuildSystem => (p: Parameters) => LazyModule(new TraceGenSystem()(p))
 })
 
 /**
@@ -107,7 +101,6 @@ class WithMultiRoCC extends Config((site, here, up) => {
  */
 class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => {
   case MultiRoCCKey => {
-    require(harts.max <= ((up(RocketTilesKey, site).length + up(BoomTilesKey, site).length) - 1))
     up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
       (i -> Seq((p: Parameters) => {
         LazyModule(new Hwacha()(p)).suggestName("hwacha")
@@ -117,38 +110,23 @@ class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => {
 })
 
 
-/**
- * Config fragment to add a small Rocket core to the system as a "control" core.
- * Used as an example of a PMU core.
- */
-class WithControlCore extends Config((site, here, up) => {
-  case RocketTilesKey => up(RocketTilesKey, site) :+
-    RocketTileParams(
-      core = RocketCoreParams(
-        useVM = false,
-        fpu = None,
-        mulDiv = Some(MulDivParams(mulUnroll = 8))),
-      btb = None,
-      dcache = Some(DCacheParams(
-        rowBits = site(SystemBusKey).beatBits,
-        nSets = 64,
-        nWays = 1,
-        nTLBEntries = 4,
-        nMSHRs = 0,
-        blockBytes = site(CacheBlockBytes))),
-      icache = Some(ICacheParams(
-        rowBits = site(SystemBusKey).beatBits,
-        nSets = 64,
-        nWays = 1,
-        nTLBEntries = 4,
-        blockBytes = site(CacheBlockBytes))),
-      hartId = up(RocketTilesKey, site).size + up(BoomTilesKey, site).size
-    )
-  case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
-})
-
 class WithTraceIO extends Config((site, here, up) => {
-  case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
-  case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true))
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
+    case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      trace = true))
+    case tp: ArianeTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      trace = true))
+    case other => other
+  }
   case TracePortKey => Some(TracePortParams())
 })
+
+class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
+  case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
+    case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(nPerfCounters = n)))
+    case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
+      core = tp.tileParams.core.copy(nPerfCounters = n)))
+    case other => other
+  }
+})

generators/chipyard/src/main/scala/DigitalTop.scala

@@ -12,7 +12,7 @@ import freechips.rocketchip.devices.tilelink._
 // ------------------------------------
 
 // DOC include start: DigitalTop
-class DigitalTop(implicit p: Parameters) extends System
+class DigitalTop(implicit p: Parameters) extends ChipyardSystem
   with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
   with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
   with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
@@ -30,7 +30,7 @@ class DigitalTop(implicit p: Parameters) extends System
   override lazy val module = new DigitalTopModule(this)
 }
 
-class DigitalTopModule[+L <: DigitalTop](l: L) extends SystemModule(l)
+class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
   with testchipip.CanHaveTraceIOModuleImp
   with testchipip.CanHavePeripheryBlockDeviceModuleImp
   with testchipip.CanHavePeripherySerialModuleImp

generators/chipyard/src/main/scala/IOBinders.scala

@@ -11,6 +11,7 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.system.{SimAXIMem}
 import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4EdgeParameters}
 import freechips.rocketchip.util._
+import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem}
 
 import sifive.blocks.devices.gpio._
 import sifive.blocks.devices.uart._
@@ -20,7 +21,6 @@ import barstools.iocell.chisel._
 
 import testchipip._
 import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey}
-import tracegen.{HasTraceGenTilesModuleImp}
 
 import scala.reflect.{ClassTag}
 
@@ -389,7 +389,7 @@ class WithSimSerial extends OverrideIOBinder({
 })
 
 class WithTraceGenSuccessBinder extends OverrideIOBinder({
-  (system: HasTraceGenTilesModuleImp) => {
+  (system: GroundTestSubsystemModuleImp[GroundTestSubsystem]) => {
     val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success"))
     successPort.suggestName("success")
     val harnessFn = (th: chipyard.TestHarness) => { when (successPort) { th.success := true.B }; Nil }

generators/chipyard/src/main/scala/Subsystem.scala

@@ -21,93 +21,36 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.subsystem._
 import freechips.rocketchip.amba.axi4._
 
-import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams}
-import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams}
+import boom.common.{BoomTile}
 
-import testchipip.{DromajoHelper}
-
-trait HasChipyardTiles extends HasTiles
-  with CanHavePeripheryPLIC
-  with CanHavePeripheryCLINT
-  with HasPeripheryDebug
-{ this: BaseSubsystem =>
-
-  val module: HasChipyardTilesModuleImp
-
-  protected val rocketTileParams = p(RocketTilesKey)
-  protected val boomTileParams = p(BoomTilesKey)
-  protected val arianeTileParams = p(ArianeTilesKey)
-
-  // crossing can either be per tile or global (aka only 1 crossing specified)
-  private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size)
-  private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size)
-  private val arianeCrossings = perTileOrGlobalSetting(p(ArianeCrossingKey), arianeTileParams.size)
-
-  val allTilesInfo = (rocketTileParams ++ boomTileParams ++ arianeTileParams) zip (rocketCrossings ++ boomCrossings ++ arianeCrossings)
-
-  // Make a tile and wire its nodes into the system,
-  // according to the specified type of clock crossing.
-  // Note that we also inject new nodes into the tile itself,
-  // also based on the crossing type.
-  // This MUST be performed in order of hartid
-  // There is something weird with registering tile-local interrupt controllers to the CLINT.
-  // TODO: investigate why
-  val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map {
-    case (param, crossing) => {
-
-      val tile = param match {
-        case r: RocketTileParams => {
-          LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
-        }
-        case b: BoomTileParams => {
-          LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
-        }
-        case a: ArianeTileParams => {
-          LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode))
-        }
-      }
-      connectMasterPortsToSBus(tile, crossing)
-      connectSlavePortsToCBus(tile, crossing)
-      connectInterrupts(tile, debugOpt, clintOpt, plicOpt)
-
-      tile
-    }
-  }
 
+import testchipip.{DromajoHelper}
 
+class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
+  with HasTiles
+{
   def coreMonitorBundles = tiles.map {
     case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle
     case b: BoomTile => b.module.core.coreMonitorBundle
   }.toList
+  override lazy val module = new ChipyardSubsystemModuleImp(this)
 }
 
-trait HasChipyardTilesModuleImp extends HasTilesModuleImp
-  with HasPeripheryDebugModuleImp
-{
-  val outer: HasChipyardTiles
-}
-
-class Subsystem(implicit p: Parameters) extends BaseSubsystem
-  with HasChipyardTiles
-{
-  override lazy val module = new SubsystemModuleImp(this)
-
-  def getOMInterruptDevice(resourceBindingsMap: ResourceBindingsMap): Seq[OMInterrupt] = Nil
-}
-
-class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
+class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
   with HasResetVectorWire
-  with HasChipyardTilesModuleImp
+  with HasTilesModuleImp
 {
-  tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
-    wire.hartid := i.U
+
+  for (i <- 0 until outer.tiles.size) {
+    val wire = tile_inputs(i)
+    wire.hartid := outer.hartIdList(i).U
     wire.reset_vector := global_reset_vector
   }
 
-  // create file with boom params
+  // create file with core params
   ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n"))
-
   // Generate C header with relevant information for Dromajo
   // This is included in the `dromajo_params.h` header file
-  DromajoHelper.addArtefacts
+  DromajoHelper.addArtefacts()
 }
+

generators/chipyard/src/main/scala/System.scala

@@ -21,20 +21,20 @@ import freechips.rocketchip.util.{DontTouch}
 /**
  * Base top with periphery devices and ports, and a BOOM + Rocket subsystem
  */
-class System(implicit p: Parameters) extends Subsystem
+class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
   with HasAsyncExtInterrupts
   with CanHaveMasterAXI4MemPort
   with CanHaveMasterAXI4MMIOPort
   with CanHaveSlaveAXI4Port
   with HasPeripheryBootROM
 {
-  override lazy val module = new SystemModule(this)
+  override lazy val module = new ChipyardSystemModule(this)
 }
 
 /**
  * Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem
  */
-class SystemModule[+L <: System](_outer: L) extends SubsystemModuleImp(_outer)
+class ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer)
   with HasRTCModuleImp
   with HasExtInterruptsModuleImp
   with HasPeripheryBootROMModuleImp