Fix spike-cosim causing problems for firesim

ucb-bar · Feb 3, 2023 · b0b0d89 · b0b0d89
1 parent adf8f79
commit b0b0d89
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Showing 3 changed files with 18 additions and 9 deletions.
diff --git a/generators/chipyard/src/main/scala/Cospike.scala b/generators/chipyard/src/main/scala/Cospike.scala
@@ -32,15 +32,19 @@ class CospikeResources(
   addResource("/vsrc/cospike.v")
 }
 
+case object SpikeCosimKey extends Field[Boolean](false)
+
 trait CanHaveSpikeCosim { this: ChipyardSystem =>
-  InModuleBody {
-    val isa = tiles.headOption.map(_.isaDTS).getOrElse("")
-    val mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0))
-    val mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0))
-    val pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0)
-    val nharts = tiles.size
-    val bootrom = bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse("")
-    val resources = Module(new CospikeResources(isa, pmpregions, mem0_base, mem0_size, nharts, bootrom))
+  if (p(SpikeCosimKey)) {
+    InModuleBody {
+      val isa = tiles.headOption.map(_.isaDTS).getOrElse("")
+      val mem0_base = p(ExtMem).map(_.master.base).getOrElse(BigInt(0))
+      val mem0_size = p(ExtMem).map(_.master.size).getOrElse(BigInt(0))
+      val pmpregions = tiles.headOption.map(_.tileParams.core.nPMPs).getOrElse(0)
+      val nharts = tiles.size
+      val bootrom = bootROM.map(_.module.contents.toArray.mkString(" ")).getOrElse("")
+      val resources = Module(new CospikeResources(isa, pmpregions, mem0_base, mem0_size, nharts, bootrom))
+    }
   }
 }
 

diff --git a/generators/chipyard/src/main/scala/config/BoomConfigs.scala b/generators/chipyard/src/main/scala/config/BoomConfigs.scala
@@ -51,6 +51,7 @@ class DromajoBoomConfig extends Config(
 
 class MediumBoomCosimConfig extends Config(
   new chipyard.harness.WithCospikeBridge ++                      // attach spike-cosim
+  new chipyard.config.EnableSpikeCosim ++                        // enable co-sim
   new chipyard.config.WithTraceIO ++                             // enable the traceio
   new boom.common.WithNMediumBooms(1) ++
   new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
@@ -9,7 +9,7 @@ import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams
 
 import boom.common.{BoomTileAttachParams}
 import cva6.{CVA6TileAttachParams}
-
+import chipyard.{SpikeCosimKey}
 import testchipip._
 
 class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
@@ -79,3 +79,7 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => {
     ))
   }
 })
+
+class EnableSpikeCosim extends Config((site, here, up) => {
+  case SpikeCosimKey => true
+})