Remove redundant ChipTop reset synchronizer

ucb-bar · Oct 28, 2020 · b0836d8 · b0836d8
1 parent 93e57ef
commit b0836d8
Showing 1 changed file with 1 addition and 3 deletions.
diff --git a/generators/chipyard/src/main/scala/Clocks.scala b/generators/chipyard/src/main/scala/Clocks.scala
@@ -28,14 +28,12 @@ object GenerateReset {
     val (reset_io, resetIOCell) = IOCell.generateIOFromSignal(async_reset_wire, "reset",
       abstractResetAsAsync = true)
 
-    val reset_wire = ResetCatchAndSync(clock, async_reset_wire.asBool())
-
     chiptop.iocells ++= resetIOCell
     chiptop.harnessFunctions += ((th: HasHarnessSignalReferences) => {
       reset_io := th.dutReset
       Nil
     })
-    reset_wire
+    async_reset_wire
   }
 }